From: Jason Gunthorpe <jgg@nvidia.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Lucas Wei <lucaswei@google.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
sjadavani@google.com, kernel test robot <lkp@intel.com>,
stable@vger.kernel.org, kernel-team@android.com,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, smostafa@google.com
Subject: Re: [PATCH v2] arm64: errata: Workaround for SI L1 downstream coherency issue
Date: Thu, 8 Jan 2026 12:54:14 -0400 [thread overview]
Message-ID: <20260108165414.GF23056@nvidia.com> (raw)
In-Reply-To: <a0fd155b-67fc-45a4-8510-01f89681d6fa@arm.com>
On Thu, Jan 08, 2026 at 04:41:47PM +0000, Robin Murphy wrote:
> The point is that if there's a coherent interconnect downstream of the SMMU
> - which we infer from the SMMU's own coherency - then we should be able to
> make the *output* of SMMU translation coherent,
Sadly I'm aware of HW where that isn't true..
The SMMU is flexible and there are more than one fabric connection
from a SW visible SMMU instance. They can have different properties.
Especially if the design is focused on something like isochronous real
time guarentees.
Jason
next prev parent reply other threads:[~2026-01-08 16:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-29 3:36 [PATCH v2] arm64: errata: Workaround for SI L1 downstream coherency issue Lucas Wei
2026-01-01 8:27 ` Kuan-Wei Chiu
2026-01-01 18:55 ` Marc Zyngier
2026-01-07 16:33 ` Will Deacon
2026-01-07 17:55 ` Robin Murphy
2026-01-08 15:18 ` Will Deacon
2026-01-08 16:13 ` Jason Gunthorpe
2026-01-08 16:41 ` Robin Murphy
2026-01-08 16:54 ` Jason Gunthorpe [this message]
2026-01-07 16:22 ` Will Deacon
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