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[123.253.188.110]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3c49037sm216111905ad.36.2026.01.13.20.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jan 2026 20:47:21 -0800 (PST) From: Nicholas Piggin To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Nicholas Piggin , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , bin.meng@windriver.com, vivahavey@gmail.com, Alvin Chang , Yu-Ming Chang , Joel Stanley Subject: [RFC PATCH 00/25] target/riscv/debug: Sdtrig fixes and TT Ascalon support Date: Wed, 14 Jan 2026 14:46:33 +1000 Message-ID: <20260114044701.1173347-1-npiggin@gmail.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, Sorry for the big series. The Ascalon CPU implements Sdtrig with 2 different types of mcontrol6 trigger and the icount trigger, so in the course of testing and bringing up OpenSBI and Linux support for this, I've accumulated quite a lot. My new year resolution is to start being better upstream contributor, it's taken me a while with changing jobs and architectures. So I don't expect others to drop everything to review this! Joel has been prodding me, and noted there is some other Sdtrig work going on with the v1.0 support patches. I think the debug v1.0 patches are somewhat orthogonal to this series, but both are addressing aspects of a common problem of Sdtrig implementation specifics. I wonder if these should be reconciled or left separate. Sdtrig v1.00/v0.13 configuration is a single boolean which is feasible as a CPU property. Whereas the entire space of Sdtrig implementation seems like too much to make configurable in that way. Any thoughts would be welcome. Thanks, Nick Nicholas Piggin (25): target/riscv/debug: Check only mcontrol triggers for break/watchpoint matching target/riscv/debug: Handle changing trigger types target/riscv/debug: Implement permissive type unavailable trigger target/riscv/debug: Fix icount trigger privilege check target/riscv/debug: Update itrigger_enabled after changing privilege target/riscv/debug: Implement get_trigger_action for icount type trigger target/riscv/debug: Fix migration post_load icount_enabled() test target/riscv/debug: Fix icount privilege matching icount_enabled() test target/riscv/debug: Implement icount trigger textra matching target/riscv/debug: Maintain itrigger_enabled in helper_itrigger_match() target/riscv/debug: Fix breakpoint matching action target/riscv/debug: Put mcontrol load/store match address into tval target/riscv/debug: Remove breakpoints on reset target/riscv/debug: Move debug CPU post_load details into debug.c target/riscv/debug: Insert breakpoints after migration target/riscv/debug: Remove itrigger icount-enabled mode target/riscv/debug: Advertise icount trigger type in tinfo target/riscv/debug: Reset trigger type to unavailable target/riscv/debug: Add new debug state format target/riscv/debug: Migrate mcontext using new sdtrig vmstate target/riscv/debug: Implementation specific Sdtrig configuration target/riscv/debug: Support heterogeneous trigger types target/riscv/debug: Support heterogeneous mcontrol access types target/riscv/debug: Emulate TT Ascalon Sdtrig target/riscv/debug: Fix minor comment typos target/riscv/cpu.c | 65 ++++- target/riscv/cpu.h | 41 ++- target/riscv/cpu_helper.c | 10 +- target/riscv/csr.c | 7 +- target/riscv/debug.c | 571 ++++++++++++++++++++----------------- target/riscv/debug.h | 19 +- target/riscv/machine.c | 96 ++++++- target/riscv/tcg/tcg-cpu.c | 5 +- 8 files changed, 510 insertions(+), 304 deletions(-) -- 2.51.0