From: Imre Deak <imre.deak@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <intel-xe@lists.freedesktop.org>
Cc: "Jouni Högander" <jouni.hogander@intel.com>
Subject: [PATCH 11/15] drm/i915/dsc: Add intel_dsc_get_slice_config()
Date: Wed, 14 Jan 2026 18:22:28 +0200 [thread overview]
Message-ID: <20260114162232.92731-12-imre.deak@intel.com> (raw)
In-Reply-To: <20260114162232.92731-1-imre.deak@intel.com>
Add intel_dsc_get_slice_config() and move the logic to select a given
slice configuration to that function from the configuration loop in
intel_dp_dsc_get_slice_count(). The same functionality can be used by
other outputs like DSI as well, done as a follow-up.
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++-------
drivers/gpu/drm/i915/display/intel_vdsc.c | 48 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.h | 4 ++
3 files changed, 59 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index eff4ea998a948..1d6009b994977 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1030,28 +1030,20 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
* TGL+: 2x4 (TODO: Add support for this)
*/
for (slices_per_pipe = 1; slices_per_pipe <= 4; slices_per_pipe++) {
- int slices_per_line = slices_per_pipe * num_joined_pipes;
+ struct intel_dsc_slice_config config;
+ int slices_per_line;
- /*
- * 3 DSC Slices per pipe need 3 DSC engines, which is supported only
- * with Ultrajoiner only for some platforms.
- */
- if (slices_per_pipe == 3 &&
- (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4))
+ if (!intel_dsc_get_slice_config(display,
+ num_joined_pipes, slices_per_pipe,
+ &config))
continue;
+ slices_per_line = intel_dsc_line_slice_count(&config);
+
if (!(drm_dp_dsc_slice_count_to_mask(slices_per_line) &
sink_slice_count_mask))
continue;
- /*
- * Bigjoiner needs small joiner to be enabled.
- * So there should be at least 2 dsc slices per pipe,
- * whenever bigjoiner is enabled.
- */
- if (num_joined_pipes > 1 && slices_per_pipe < 2)
- continue;
-
if (mode_hdisplay % slices_per_line)
continue;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d213947103b51..fd3b4fc85e557 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -40,6 +40,54 @@ int intel_dsc_line_slice_count(const struct intel_dsc_slice_config *config)
return config->pipes_per_line * config->streams_per_pipe * config->slices_per_stream;
}
+bool intel_dsc_get_slice_config(struct intel_display *display,
+ int pipes_per_line, int slices_per_pipe,
+ struct intel_dsc_slice_config *config)
+{
+ int streams_per_pipe;
+
+ /* TODO: Add support for 8 slices per pipe on TGL+. */
+ switch (slices_per_pipe) {
+ case 3:
+ /*
+ * 3 DSC Slices per pipe need 3 DSC engines, which is supported only
+ * with Ultrajoiner only for some platforms.
+ */
+ if (!HAS_DSC_3ENGINES(display) || pipes_per_line != 4)
+ return false;
+
+ streams_per_pipe = 3;
+ break;
+ case 4:
+ /* TODO: Consider using 1 DSC engine stream x 4 slices instead. */
+ case 2:
+ /* TODO: Consider using 1 DSC engine stream x 2 slices instead. */
+ streams_per_pipe = 2;
+ break;
+ case 1:
+ /*
+ * Bigjoiner needs small joiner to be enabled.
+ * So there should be at least 2 dsc slices per pipe,
+ * whenever bigjoiner is enabled.
+ */
+ if (pipes_per_line > 1)
+ return false;
+
+ streams_per_pipe = 1;
+ break;
+ default:
+ MISSING_CASE(slices_per_pipe);
+ return false;
+ }
+
+ config->pipes_per_line = pipes_per_line;
+ config->streams_per_pipe = streams_per_pipe;
+ config->slices_per_stream = slices_per_pipe / streams_per_pipe;
+
+ return true;
+}
+
+
static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
{
struct intel_display *display = to_intel_display(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index e61116d5297c8..aeb17670307b1 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -13,11 +13,15 @@ struct drm_printer;
enum transcoder;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_display;
struct intel_dsc_slice_config;
struct intel_encoder;
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state);
int intel_dsc_line_slice_count(const struct intel_dsc_slice_config *config);
+bool intel_dsc_get_slice_config(struct intel_display *display,
+ int num_joined_pipes, int slice_per_pipe,
+ struct intel_dsc_slice_config *config);
void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state);
void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
--
2.49.1
next prev parent reply other threads:[~2026-01-14 16:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-14 16:22 [PATCH 00/15] drm/i915/dp: Clean up link BW/DSC slice config computation (DSC slice) Imre Deak
2026-01-14 16:22 ` [PATCH 01/15] drm/i915/dsc: Track the detaild DSC slice configuration Imre Deak
2026-01-14 16:22 ` [PATCH 02/15] drm/i915/dsc: Track the DSC stream count in the DSC slice config state Imre Deak
2026-01-14 16:22 ` [PATCH 03/15] drm/i915/dsi: Move initialization of DSI DSC streams-per-pipe to fill_dsc() Imre Deak
2026-01-14 16:22 ` [PATCH 04/15] drm/i915/dsi: Track the detailed DSC slice configuration Imre Deak
2026-01-14 16:22 ` [PATCH 05/15] drm/i915/dp: " Imre Deak
2026-01-14 16:22 ` [PATCH 06/15] drm/i915/dsc: Switch to using intel_dsc_line_slice_count() Imre Deak
2026-01-14 16:22 ` [PATCH 07/15] drm/i915/dp: Factor out intel_dp_dsc_min_slice_count() Imre Deak
2026-01-14 16:22 ` [PATCH 08/15] drm/i915/dp: Use int for DSC slice count variables Imre Deak
2026-01-14 16:22 ` [PATCH 09/15] drm/i915/dp: Rename test_slice_count to slices_per_line Imre Deak
2026-01-14 16:22 ` [PATCH 10/15] drm/i915/dp: Simplify the DSC slice config loop's slices-per-pipe iteration Imre Deak
2026-01-14 16:22 ` Imre Deak [this message]
2026-01-14 16:22 ` [PATCH 12/15] drm/i915/dsi: Use intel_dsc_get_slice_config() Imre Deak
2026-01-14 16:22 ` [PATCH 13/15] drm/i915/dp: Unify DP and eDP slice count computation Imre Deak
2026-01-14 16:22 ` [PATCH 14/15] drm/i915/dp: Add intel_dp_dsc_get_slice_config() Imre Deak
2026-01-14 16:22 ` [PATCH 15/15] drm/i915/dp: Use intel_dp_dsc_get_slice_config() Imre Deak
2026-01-14 16:33 ` ✗ CI.checkpatch: warning for drm/i915/dp: Clean up link BW/DSC slice config computation (DSC slice) Patchwork
2026-01-14 16:35 ` ✓ CI.KUnit: success " Patchwork
2026-01-14 16:52 ` ✗ CI.checksparse: warning " Patchwork
2026-01-14 17:21 ` ✓ Xe.CI.BAT: success " Patchwork
2026-01-14 19:08 ` ✓ i915.CI.BAT: " Patchwork
2026-01-14 23:26 ` ✗ Xe.CI.Full: failure " Patchwork
2026-01-14 23:56 ` ✗ i915.CI.Full: " Patchwork
2026-01-15 18:36 ` Imre Deak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260114162232.92731-12-imre.deak@intel.com \
--to=imre.deak@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jouni.hogander@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.