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Cc: Ankit Nautiyal Reviewed-by: Jouni Högander # v1 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_bios.c | 6 ++---- drivers/gpu/drm/i915/display/intel_display_types.h | 1 - drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------ drivers/gpu/drm/i915/display/intel_vdsc.c | 9 +++++---- 4 files changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 8fcfdb2e1c74e..a007fcf6e1a8e 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3597,14 +3597,12 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, crtc_state->dsc.slice_config.slices_per_stream = 1; } - crtc_state->dsc.slice_count = intel_dsc_line_slice_count(&crtc_state->dsc.slice_config); - if (crtc_state->hw.adjusted_mode.crtc_hdisplay % - crtc_state->dsc.slice_count != 0) + intel_dsc_line_slice_count(&crtc_state->dsc.slice_config) != 0) drm_dbg_kms(display->drm, "VBT: DSC hdisplay %d not divisible by slice count %d\n", crtc_state->hw.adjusted_mode.crtc_hdisplay, - crtc_state->dsc.slice_count); + intel_dsc_line_slice_count(&crtc_state->dsc.slice_config)); /* * The VBT rc_buffer_block_size and rc_buffer_size definitions diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4f73a41f02984..07b626d227485 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1340,7 +1340,6 @@ struct intel_crtc_state { } slice_config; /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ u16 compressed_bpp_x16; - u8 slice_count; struct drm_dsc_config config; } dsc; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3b62d16403f27..3a12156cd6e56 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2032,12 +2032,14 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, } else { unsigned long bw_overhead_flags = pipe_config->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; + int line_slice_count = + intel_dsc_line_slice_count(&pipe_config->dsc.slice_config); if (!is_bw_sufficient_for_dsc_config(intel_dp, link_rate, lane_count, adjusted_mode->crtc_clock, adjusted_mode->hdisplay, - pipe_config->dsc.slice_count, + line_slice_count, dsc_bpp_x16, bw_overhead_flags)) continue; @@ -2428,11 +2430,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->dsc.slice_config.pipes_per_line / pipe_config->dsc.slice_config.streams_per_pipe; - pipe_config->dsc.slice_count = - intel_dsc_line_slice_count(&pipe_config->dsc.slice_config); - drm_WARN_ON(display->drm, - pipe_config->dsc.slice_count != slices_per_line); + intel_dsc_line_slice_count(&pipe_config->dsc.slice_config) != slices_per_line); ret = intel_dp_dsc_compute_params(connector, pipe_config); if (ret < 0) { @@ -2450,7 +2449,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", pipe_config->pipe_bpp, FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), - pipe_config->dsc.slice_count); + intel_dsc_line_slice_count(&pipe_config->dsc.slice_config)); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 4a3d505338cb9..d213947103b51 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -283,8 +283,9 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) int ret; vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; - vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, - pipe_config->dsc.slice_count); + vdsc_cfg->slice_width = + DIV_ROUND_UP(vdsc_cfg->pic_width, + intel_dsc_line_slice_count(&pipe_config->dsc.slice_config)); err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg); @@ -1042,7 +1043,7 @@ static void intel_vdsc_dump_state(struct drm_printer *p, int indent, drm_printf_indent(p, indent, "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n", FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), - crtc_state->dsc.slice_count, + intel_dsc_line_slice_count(&crtc_state->dsc.slice_config), crtc_state->dsc.slice_config.streams_per_pipe); } @@ -1078,7 +1079,7 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); int htotal = crtc_state->hw.adjusted_mode.crtc_htotal; - int dsc_slices = crtc_state->dsc.slice_count; + int dsc_slices = intel_dsc_line_slice_count(&crtc_state->dsc.slice_config); int pixel_rate; int min_cdclk; -- 2.49.1