From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C370ED2ECF7 for ; Tue, 20 Jan 2026 09:30:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vi83b-0003IQ-AK; Tue, 20 Jan 2026 04:29:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83Z-0003Fw-LN; Tue, 20 Jan 2026 04:29:49 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83X-0005eG-9j; Tue, 20 Jan 2026 04:29:49 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 17:29:39 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 17:29:39 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Date: Tue, 20 Jan 2026 17:29:25 +0800 Message-ID: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org This series improves AST2700 platform support by aligning SSP/TSP power and reset behavior with hardware, and enabling DRAM remapping required for proper firmware boot flow. v1: 1. The changes move DRAM/SDMC initialization earlier to support memory aliasing, add DRAM aliases for SSP/TSP SDRAM remap, and implement SSP/TSP reset, power-on, and remap controls via SCU registers. 2. With these updates, SSP and TSP can be booted via PSP and load their binaries from DRAM. Functional tests and documentation are updated accordingly. Jamin Lin (11): hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM docs: Add support vbootrom and update Manual boot for ast2700fc docs/system/arm/aspeed.rst | 37 ++- include/hw/misc/aspeed_scu.h | 6 + hw/arm/aspeed_ast27x0-fc.c | 4 + hw/arm/aspeed_ast27x0-ssp.c | 13 + hw/arm/aspeed_ast27x0-tsp.c | 10 + hw/arm/aspeed_ast27x0.c | 46 +-- hw/misc/aspeed_scu.c | 268 +++++++++++++++++- .../aarch64/test_aspeed_ast2700fc.py | 35 ++- 8 files changed, 378 insertions(+), 41 deletions(-) -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0245AD2ED0F for ; Tue, 20 Jan 2026 09:30:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vi83b-0003JV-V4; Tue, 20 Jan 2026 04:29:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83Z-0003Fw-LN; Tue, 20 Jan 2026 04:29:49 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83X-0005eG-9j; Tue, 20 Jan 2026 04:29:49 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 17:29:39 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 17:29:39 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Date: Tue, 20 Jan 2026 17:29:25 +0800 Message-ID: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series improves AST2700 platform support by aligning SSP/TSP power and reset behavior with hardware, and enabling DRAM remapping required for proper firmware boot flow. v1: 1. The changes move DRAM/SDMC initialization earlier to support memory aliasing, add DRAM aliases for SSP/TSP SDRAM remap, and implement SSP/TSP reset, power-on, and remap controls via SCU registers. 2. With these updates, SSP and TSP can be booted via PSP and load their binaries from DRAM. Functional tests and documentation are updated accordingly. Jamin Lin (11): hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM docs: Add support vbootrom and update Manual boot for ast2700fc docs/system/arm/aspeed.rst | 37 ++- include/hw/misc/aspeed_scu.h | 6 + hw/arm/aspeed_ast27x0-fc.c | 4 + hw/arm/aspeed_ast27x0-ssp.c | 13 + hw/arm/aspeed_ast27x0-tsp.c | 10 + hw/arm/aspeed_ast27x0.c | 46 +-- hw/misc/aspeed_scu.c | 268 +++++++++++++++++- .../aarch64/test_aspeed_ast2700fc.py | 35 ++- 8 files changed, 378 insertions(+), 41 deletions(-) -- 2.43.0