From: kernel test robot <lkp@intel.com>
To: Rishikesh Jethwani <rjethwani@purestorage.com>, netdev@vger.kernel.org
Cc: oe-kbuild-all@lists.linux.dev, saeedm@nvidia.com,
tariqt@nvidia.com, mbloch@nvidia.com, borisp@nvidia.com,
john.fastabend@gmail.com, kuba@kernel.org, sd@queasysnail.net,
davem@davemloft.net, pabeni@redhat.com, edumazet@google.com,
leon@kernel.org, Rishikesh Jethwani <rjethwani@purestorage.com>
Subject: Re: [PATCH v4 2/3] tls: add hardware offload key update support
Date: Thu, 22 Jan 2026 13:15:08 +0800 [thread overview]
Message-ID: <202601221215.VSoxPBxE-lkp@intel.com> (raw)
In-Reply-To: <20260121215727.3994324-3-rjethwani@purestorage.com>
Hi Rishikesh,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.19-rc6 next-20260121]
[cannot apply to horms-ipvs/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Rishikesh-Jethwani/tls-add-TLS-1-3-hardware-offload-support/20260122-060724
base: linus/master
patch link: https://lore.kernel.org/r/20260121215727.3994324-3-rjethwani%40purestorage.com
patch subject: [PATCH v4 2/3] tls: add hardware offload key update support
config: parisc-allmodconfig (https://download.01.org/0day-ci/archive/20260122/202601221215.VSoxPBxE-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260122/202601221215.VSoxPBxE-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601221215.VSoxPBxE-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from arch/parisc/include/asm/atomic.h:11,
from include/linux/atomic.h:7,
from include/crypto/aead.h:11,
from net/tls/tls_device.c:32:
net/tls/tls_device.c: In function 'tls_set_device_offload':
>> arch/parisc/include/asm/barrier.h:36:28: error: field '__val' declared as a function
36 | union { typeof(*p) __val; char __c[1]; } __u = \
| ^~~~~
include/asm-generic/barrier.h:172:55: note: in expansion of macro '__smp_store_release'
172 | #define smp_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
| ^~~~~~~~~~~~~~~~~~~
net/tls/tls_device.c:1249:25: note: in expansion of macro 'smp_store_release'
1249 | smp_store_release(sk->sk_validate_xmit_skb,
| ^~~~~~~~~~~~~~~~~
>> arch/parisc/include/asm/barrier.h:37:28: error: cast specifies function type
37 | { .__val = (__force typeof(*p)) (v) }; \
| ^
include/asm-generic/barrier.h:172:55: note: in expansion of macro '__smp_store_release'
172 | #define smp_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
| ^~~~~~~~~~~~~~~~~~~
net/tls/tls_device.c:1249:25: note: in expansion of macro 'smp_store_release'
1249 | smp_store_release(sk->sk_validate_xmit_skb,
| ^~~~~~~~~~~~~~~~~
--
In file included from arch/parisc/include/asm/atomic.h:11,
from include/linux/atomic.h:7,
from include/crypto/aead.h:11,
from tls_device.c:32:
tls_device.c: In function 'tls_set_device_offload':
>> arch/parisc/include/asm/barrier.h:36:28: error: field '__val' declared as a function
36 | union { typeof(*p) __val; char __c[1]; } __u = \
| ^~~~~
include/asm-generic/barrier.h:172:55: note: in expansion of macro '__smp_store_release'
172 | #define smp_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
| ^~~~~~~~~~~~~~~~~~~
tls_device.c:1249:25: note: in expansion of macro 'smp_store_release'
1249 | smp_store_release(sk->sk_validate_xmit_skb,
| ^~~~~~~~~~~~~~~~~
>> arch/parisc/include/asm/barrier.h:37:28: error: cast specifies function type
37 | { .__val = (__force typeof(*p)) (v) }; \
| ^
include/asm-generic/barrier.h:172:55: note: in expansion of macro '__smp_store_release'
172 | #define smp_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
| ^~~~~~~~~~~~~~~~~~~
tls_device.c:1249:25: note: in expansion of macro 'smp_store_release'
1249 | smp_store_release(sk->sk_validate_xmit_skb,
| ^~~~~~~~~~~~~~~~~
vim +/__val +36 arch/parisc/include/asm/barrier.h
fedb8da96355f5f John David Anglin 2018-08-05 32
e96ebd589debd9a John David Anglin 2020-07-30 33 #define __smp_store_release(p, v) \
e96ebd589debd9a John David Anglin 2020-07-30 34 do { \
e96ebd589debd9a John David Anglin 2020-07-30 35 typeof(p) __p = (p); \
e96ebd589debd9a John David Anglin 2020-07-30 @36 union { typeof(*p) __val; char __c[1]; } __u = \
e96ebd589debd9a John David Anglin 2020-07-30 @37 { .__val = (__force typeof(*p)) (v) }; \
e96ebd589debd9a John David Anglin 2020-07-30 38 compiletime_assert_atomic_type(*p); \
e96ebd589debd9a John David Anglin 2020-07-30 39 switch (sizeof(*p)) { \
e96ebd589debd9a John David Anglin 2020-07-30 40 case 1: \
e96ebd589debd9a John David Anglin 2020-07-30 41 asm volatile("stb,ma %0,0(%1)" \
e96ebd589debd9a John David Anglin 2020-07-30 42 : : "r"(*(__u8 *)__u.__c), "r"(__p) \
e96ebd589debd9a John David Anglin 2020-07-30 43 : "memory"); \
e96ebd589debd9a John David Anglin 2020-07-30 44 break; \
e96ebd589debd9a John David Anglin 2020-07-30 45 case 2: \
e96ebd589debd9a John David Anglin 2020-07-30 46 asm volatile("sth,ma %0,0(%1)" \
e96ebd589debd9a John David Anglin 2020-07-30 47 : : "r"(*(__u16 *)__u.__c), "r"(__p) \
e96ebd589debd9a John David Anglin 2020-07-30 48 : "memory"); \
e96ebd589debd9a John David Anglin 2020-07-30 49 break; \
e96ebd589debd9a John David Anglin 2020-07-30 50 case 4: \
e96ebd589debd9a John David Anglin 2020-07-30 51 asm volatile("stw,ma %0,0(%1)" \
e96ebd589debd9a John David Anglin 2020-07-30 52 : : "r"(*(__u32 *)__u.__c), "r"(__p) \
e96ebd589debd9a John David Anglin 2020-07-30 53 : "memory"); \
e96ebd589debd9a John David Anglin 2020-07-30 54 break; \
e96ebd589debd9a John David Anglin 2020-07-30 55 case 8: \
e96ebd589debd9a John David Anglin 2020-07-30 56 if (IS_ENABLED(CONFIG_64BIT)) \
e96ebd589debd9a John David Anglin 2020-07-30 57 asm volatile("std,ma %0,0(%1)" \
e96ebd589debd9a John David Anglin 2020-07-30 58 : : "r"(*(__u64 *)__u.__c), "r"(__p) \
e96ebd589debd9a John David Anglin 2020-07-30 59 : "memory"); \
e96ebd589debd9a John David Anglin 2020-07-30 60 break; \
e96ebd589debd9a John David Anglin 2020-07-30 61 } \
e96ebd589debd9a John David Anglin 2020-07-30 62 } while (0)
e96ebd589debd9a John David Anglin 2020-07-30 63
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2026-01-22 5:15 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-21 21:57 [PATCH v4 0/3] tls: Add TLS 1.3 hardware offload support Rishikesh Jethwani
2026-01-21 21:57 ` [PATCH v4 1/3] tls: add " Rishikesh Jethwani
2026-01-21 21:57 ` [PATCH v4 2/3] tls: add hardware offload key update support Rishikesh Jethwani
2026-01-22 4:09 ` kernel test robot
2026-01-22 5:15 ` kernel test robot [this message]
2026-01-22 7:19 ` kernel test robot
2026-01-22 7:54 ` kernel test robot
2026-01-21 21:57 ` [PATCH v4 3/3] mlx5: TLS 1.3 hardware offload support Rishikesh Jethwani
2026-01-22 11:30 ` [PATCH v4 0/3] tls: Add " Tariq Toukan
2026-01-22 19:22 ` Rishikesh Jethwani
2026-01-23 19:05 ` Rishikesh Jethwani
2026-01-26 23:37 ` Rishikesh Jethwani
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