From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 549DE344DB7 for ; Wed, 28 Jan 2026 23:17:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769642262; cv=none; b=sx0DogaMes5+GqRNXYFKEUcD205QRwm+bN9HM218ciIIwpBeXSQe91uBcPEt0q4a+KMoD2WjJC8cmclzc9b4UCKh84m6FYDU2BStcfViwfr5wXs4PHakk4SZ/0l2njaOmCcU5nYOW7gzCwifdfynnfJLmsyK1YiNnzw92ysjtlg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769642262; c=relaxed/simple; bh=Nqtv2gWxm8W+8gxjUvMBaqTGy6CDVIMjftYYH4JtDuY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q6boJ3WY9sf97Z6UxqNwx5d1MS216GkJvY46pZyQTsJqWU3I/S3UqGjwxlQ4UrmSFismYoJ8w4c6nFLXBwisspQMl+qj/kpRTVDXLRuNweh/vgpB00UnE7sytCO7PNUarQmZ1Y/OoG4L2ogirGHwi8ijo5MF7yJgAFOX/4P+KSY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=es4azEx7; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="es4azEx7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769642261; x=1801178261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nqtv2gWxm8W+8gxjUvMBaqTGy6CDVIMjftYYH4JtDuY=; b=es4azEx7p+kI9/zyQ5Fox0exWkUmBrjrKCQOERCo0PSPGDkrtqoqBAGP Apao63xC1jYoA4qwxX/6acqdW3dtSrBBt2KD19yKzfIWCPZ4Fv1K2Jty/ RkgimlF/cl7NtHfZkroo+nO4NeQKQJbxlTL8Rd20haZeC+AIP7D7lEAQT mLFsgcL+rlsgaP5Jx3krMOZRPXVDoAWcqAgZ9/xpXeJFPHsgIV7+tphNe 5kYdUU1K3LlnsJDAT5NbXwfPNX8c7B1YovtGm34OjvwWUHt2BvtbEJe2P U9t3bZDlugccxkbNURxQ2Aar1YhjKFa94cTva4ASaTb+XPqefdxlshVom w==; X-CSE-ConnectionGUID: 8vG4PtEVSKajlWFUVhFWRA== X-CSE-MsgGUID: dSY73bJ3TP+xYObZ1kHUWw== X-IronPort-AV: E=McAfee;i="6800,10657,11685"; a="73462329" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="73462329" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 15:17:40 -0800 X-CSE-ConnectionGUID: gD39TRv0RxC2vmW5Pk31AA== X-CSE-MsgGUID: U5A0iZnPTZ2eh10rtiNbUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208001775" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 15:17:39 -0800 From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V2 06/11] target/i386: Save/Restore DS based PEBS specfic MSRs Date: Wed, 28 Jan 2026 15:09:43 -0800 Message-ID: <20260128231003.268981-7-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128231003.268981-1-zide.chen@intel.com> References: <20260128231003.268981-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Dapeng Mi DS-based PEBS introduces three MSRs: MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, and MSR_IA32_PEBS_ENABLE. Save and restore these MSRs when legacy DS PEBS is enabled. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - No changes. target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 25 +++++++++++++++++++++++++ target/i386/machine.c | 27 ++++++++++++++++++++++++++- 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 812d53e22c41..3e2222e105bc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -422,6 +422,7 @@ typedef enum X86Seg { #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT 0x3f #define PERF_CAP_FULL_WRITE (1U << 13) +#define PERF_CAP_PEBS_BASELINE (1U << 14) #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -512,6 +513,11 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 +/* Legacy DS based PEBS MSRs */ +#define MSR_IA32_PEBS_ENABLE 0x3f1 +#define MSR_PEBS_DATA_CFG 0x3f2 +#define MSR_IA32_DS_AREA 0x600 + #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 @@ -2089,6 +2095,9 @@ typedef struct CPUArchState { uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; + uint64_t msr_ds_area; + uint64_t msr_pebs_data_cfg; + uint64_t msr_pebs_enable; uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; uint64_t msr_gp_counters[MAX_GP_COUNTERS]; uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a2cf9b5df35d..a72e4d60dfa2 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4143,6 +4143,15 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); } + if (env->features[FEAT_1_EDX] & CPUID_DTS) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, env->msr_ds_area); + } + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_PEBS_BASELINE) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, env->msr_pebs_enable); + kvm_msr_entry_add(cpu, MSR_PEBS_DATA_CFG, env->msr_pebs_data_cfg); + } + /* Set the counter values. */ for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, @@ -4688,6 +4697,13 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, perf_cntr_base + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } + if (env->features[FEAT_1_EDX] & CPUID_DTS) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0); + } + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_PEBS_BASELINE) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, 0); + kvm_msr_entry_add(cpu, MSR_PEBS_DATA_CFG, 0); + } } if (env->mcg_cap) { @@ -5013,6 +5029,15 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; break; + case MSR_IA32_DS_AREA: + env->msr_ds_area = msrs[i].data; + break; + case MSR_PEBS_DATA_CFG: + env->msr_pebs_data_cfg = msrs[i].data; + break; + case MSR_IA32_PEBS_ENABLE: + env->msr_pebs_enable = msrs[i].data; + break; case HV_X64_MSR_HYPERCALL: env->msr_hv_hypercall = msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 7d08a05835fc..7f45db1247b1 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -659,6 +659,27 @@ static const VMStateDescription vmstate_msr_ia32_feature_control = { } }; +static bool ds_pebs_enabled(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return (env->msr_ds_area || env->msr_pebs_enable || + env->msr_pebs_data_cfg); +} + +static const VMStateDescription vmstate_msr_ds_pebs = { + .name = "cpu/msr_ds_pebs", + .version_id = 1, + .minimum_version_id = 1, + .needed = ds_pebs_enabled, + .fields = (const VMStateField[]){ + VMSTATE_UINT64(env.msr_ds_area, X86CPU), + VMSTATE_UINT64(env.msr_pebs_data_cfg, X86CPU), + VMSTATE_UINT64(env.msr_pebs_enable, X86CPU), + VMSTATE_END_OF_LIST()} +}; + static bool pmu_enable_needed(void *opaque) { X86CPU *cpu = opaque; @@ -697,7 +718,11 @@ static const VMStateDescription vmstate_msr_architectural_pmu = { VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), VMSTATE_END_OF_LIST() - } + }, + .subsections = (const VMStateDescription * const []) { + &vmstate_msr_ds_pebs, + NULL, + }, }; static bool mpx_needed(void *opaque) -- 2.52.0