From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 975B2356A2C for ; Mon, 2 Feb 2026 10:14:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.92.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770027277; cv=none; b=PEUIR4h0dhX09NL31Zyysi1iucifsQLtNWT+Y7WCSW2q66GU8gyt9S4sygbIZCPXiiaDfHacF6ezVi7NaejtZjWSl6HQOhrx4n6YaiGKfbeTLydd5kBQacP9z7R88oBn71IxFpucOFJbuV2dfwCVc3qc0qhH5VNs2ktW4NRWvis= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770027277; c=relaxed/simple; bh=PihId54s7mYrRdtOxjc7XOtwV+V7nPtKQrl5VJBtlHs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=I+AqN5mzjY8mOyHTi3YNgbzEI5M+WJr092bvD1evdoErAQ90XERfcytdwEA4jrTyyX2m7ppyECmoRfrkax1f+y45ybWZTE1WzcsTjrqnQ5VsOMo7jV0XSohn63qyAO6UCUaXDnKhfypGtHq9MNpLWa4tEfNRBwFOb2+Dpjf0LoA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=c3r3nX5l; arc=none smtp.client-ip=90.155.92.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="c3r3nX5l" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=X0v2xyxn4pJvlXjun7ddt3/MeAG/dEd9ltAJ9Nb5Tbw=; b=c3r3nX5l2aYjwQKJf3MWCfVbRg txr01UqMXy3U4i2FC8xocKOgzJ7SiLuyvMuy3Zts6/dM2YCBobB2i5/tvXi2QttueBMzgMF2GxXFl fhzK7D0iXPcN4qoEbgylL7uvar0sX15IITZIIZGG4iSUOYEwpFfC2R1QPDlN70i4KDjhvgzT829iT h1RfTqSYakHO1DBgXP1W22qoZUu+v/aEVuLowU1Sy2e8lmq8JG8gFY40bwAKkDiXl5lzjXxHfgbvF /f8ZjRAc9/4lxzDOcxFqCxoQH5SllDUWpLrZmN6Get547g6qN+n1LkFCDHb7kP9GoGcvLCZ+a+NIh T0LYCmdw==; Received: from 2001-1c00-8d85-5700-266e-96ff-fe07-7dcc.cable.dynamic.v6.ziggo.nl ([2001:1c00:8d85:5700:266e:96ff:fe07:7dcc] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.98.2 #2 (Red Hat Linux)) id 1vmqww-0000000EF98-3cHx; Mon, 02 Feb 2026 10:14:31 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 84004303031; Mon, 02 Feb 2026 11:14:24 +0100 (CET) Date: Mon, 2 Feb 2026 11:14:24 +0100 From: Peter Zijlstra To: Thomas Gleixner Cc: LKML , Ihor Solodrai , Shrikanth Hegde , Mathieu Desnoyers , Michael Jeanson Subject: Re: [patch V2 0/4] sched/mmcid: Cure mode transition woes Message-ID: <20260202101424.GB3016024@noisy.programming.kicks-ass.net> References: <20260201192234.380608594@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260201192234.380608594@kernel.org> On Mon, Feb 02, 2026 at 10:39:35AM +0100, Thomas Gleixner wrote: > --- a/kernel/sched/core.c > +++ b/kernel/sched/core.c > @@ -10445,6 +10445,12 @@ static bool mm_update_max_cids(struct mm > > /* Flip the mode and set the transition flag to bridge the transfer */ > WRITE_ONCE(mc->mode, mc->mode ^ (MM_CID_TRANSIT | MM_CID_ONCPU)); > + /* > + * Order the store against the subsequent fixups so that > + * acquire(rq::lock) cannot be reordered by the CPU before the > + * store. > + */ > + smp_mb(); > return true; > } > > @@ -10487,6 +10493,16 @@ static inline void mm_update_cpus_allowe > irq_work_queue(&mc->irq_work); > } > > +static inline void mm_cid_complete_transit(struct mm_struct *mm, unsigned int mode) > +{ > + /* > + * Ensure that the store removing the TRANSIT bit cannot be > + * reordered by the CPU before the fixups have been completed. > + */ > + smp_mb(); > + WRITE_ONCE(mm->mm_cid.mode, mode); > +} I think this could've been smp_store_release(), but this is the slow path so nobody cares and this is nicely symmetric.