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[80.230.34.155]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43618057f93sm5990903f8f.24.2026.02.04.04.29.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 04:29:08 -0800 (PST) Date: Wed, 4 Feb 2026 07:29:05 -0500 From: "Michael S. Tsirkin" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Marcel Apfelbaum , Jason Wang , Gustavo Romero , Paolo Bonzini , Peter Maydell Subject: Re: [PATCH] hw/pci: Use correct bus aperture for device container size Message-ID: <20260204071045-mutt-send-email-mst@kernel.org> References: <20251124114754.79831-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20251124114754.79831-1-philmd@linaro.org> Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Nov 24, 2025 at 12:47:54PM +0100, Philippe Mathieu-Daudé wrote: > Before commit 3716d5902d7 ("pci: introduce a bus master container") > device view of the bus address space was correctly sized to the > bus aperture, but then it always used a 64-bit aperture. Restore > the previous behavior, so devices on 32-bit PCI only see 32-bit > address space. > > Signed-off-by: Philippe Mathieu-Daudé Wait I am confused. Is there a problem this is trying to fix? > --- > hw/pci/pci.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > index b1eba348e06..64f33b9de04 100644 > --- a/hw/pci/pci.c > +++ b/hw/pci/pci.c > @@ -1375,7 +1375,8 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, > pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); > > memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), > - "bus master container", UINT64_MAX); > + "bus master container", > + memory_region_size(bus->address_space_mem)); as far as I can tell this does more than it says it does. Look at raven.c: h->bus = pci_register_root_bus(d, NULL, raven_set_irq, raven_map_irq, s, &s->pci_memory, &s->pci_io, 0, 4, TYPE_PCI_BUS); The bus is created with &s->pci_memory (1G) as the address space. But the actual bus master space (&s->bm at line 285) is 4 G. Your patch limits DMA to 1G. No? failures here (definitely the ppc one) https://gitlab.com/mstredhat/qemu/-/jobs/12984084992 reverting fixed it: https://gitlab.com/mstredhat/qemu/-/jobs/12984187692 > address_space_init(&pci_dev->bus_master_as, > &pci_dev->bus_master_container_region, pci_dev->name); > pci_dev->bus_master_as.max_bounce_buffer_size = > -- > 2.51.0