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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fXP29gAP3F48fMJQpOQWP2rdu9MZ2qGpeP2NhOo4qHDBlwrQHz4hSi+WlcwS08MfyP1WvjubL/1yygeOi+9GhXp58YuhS1lElSIj2BvWufTw0Iwpzn2K/2Mgg2Fi7LJY2Gv3iHsaTlKzhA1rDDJP32f32GJb/y8Cm9Zeel3LfrB3cH+JMGuh1FqrfpECQpxRZerxpVoOiiT25Ns0js2Eg8MoEDul6s3IhEMpZ9ufs+O37EXpGr+m95L1kwaf56eErM4XCPwBxnqD6KgGd9Wgdgu6Et/XIX7EbhciRYg2P6f2XfzDIsro5ia0vecalTVpa0LZaoaZ2CjuWncV3XdBYDsebg+UmTMs4lxVT0rB4d5dZL8PcyKLclcqpb9+T8NN2Ce82gbcIFTavHR9/qvPPWySjRRHYkNrXyuwFgaQRR7AzREfGs6b9vq+2q8+mk9U X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2026 07:45:40.6370 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30343c89-1ba4-45f9-59dc-08de63c164f8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5863 From: Santosh Shukla Local interrupts can be extended to include more LVT registers in order to allow additional interrupt sources, like Instruction Based Sampling (IBS). The Extended APIC feature register indicates the number of extended Local Vector Table (LVT) registers in the local APIC. Currently, there are 4 extended LVT registers available which are located at APIC offsets (500h-530h). Future AMD processors may expose up to 255 extended LVT registers. The AVIC_EXTLVT (Extended LVT AVIC acceleration support) feature bit changes the behavior associated with reading and writing an extended LVT register when AVIC is enabled. When the AVIC_EXTLVT and AVIC are enabled, a write to an extended LVT register changes from a fault style #VMEXIT to a trap style #VMEXIT and a read of an extended LVT register no longer triggers a #VMEXIT [1]. Presence of the AVIC_EXTLVT feature is indicated via CPUID function 0x8000000A_EDX[27]. [1]: AMD Programmer's Manual Volume 2, Table 15-22. Guest vAPIC Register Access Behavior. https://bugzilla.kernel.org/attachment.cgi?id=306250 Acked-by: Borislav Petkov (AMD) Signed-off-by: Santosh Shukla Signed-off-by: Manali Shukla --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 81f7b3b91986..52882d794b3c 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -381,6 +381,7 @@ #define X86_FEATURE_X2AVIC (15*32+18) /* "x2avic" Virtual x2apic */ #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* "v_spec_ctrl" Virtual SPEC_CTRL */ #define X86_FEATURE_VNMI (15*32+25) /* "vnmi" Virtual NMI */ +#define X86_FEATURE_AVIC_EXTLVT (15*32+27) /* Extended LVT AVIC acceleration support */ #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* SVME addr check */ #define X86_FEATURE_BUS_LOCK_THRESHOLD (15*32+29) /* Bus lock threshold */ #define X86_FEATURE_IDLE_HLT (15*32+30) /* IDLE HLT intercept */ -- 2.43.0