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From: kernel test robot <lkp@intel.com>
To: Yushan Wang <wangyushan12@huawei.com>,
	alexandre.belloni@bootlin.com, arnd@arndb.de, fustini@kernel.org,
	Jonathan.Cameron@huawei.com, krzk@kernel.org,
	linus.walleij@linaro.org, will@kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: oe-kbuild-all@lists.linux.dev, fanghao11@huawei.com,
	linuxarm@huawei.com, liuyonglong@huawei.com,
	prime.zeng@hisilicon.com, wangzhou1@hisilicon.com,
	xuwei5@hisilicon.com, wangyushan12@huawei.com
Subject: Re: [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC
Date: Wed, 4 Feb 2026 10:47:00 +0800	[thread overview]
Message-ID: <202602041006.7Hb46Sl8-lkp@intel.com> (raw)
In-Reply-To: <20260203161843.649417-2-wangyushan12@huawei.com>

Hi Yushan,

kernel test robot noticed the following build errors:

[auto build test ERROR on linus/master]
[also build test ERROR on v6.19-rc8]
[cannot apply to soc/for-next next-20260203]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Yushan-Wang/soc-cache-L3-cache-driver-for-HiSilicon-SoC/20260204-004656
base:   linus/master
patch link:    https://lore.kernel.org/r/20260203161843.649417-2-wangyushan12%40huawei.com
patch subject: [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC
config: loongarch-randconfig-r131-20260204 (https://download.01.org/0day-ci/archive/20260204/202602041006.7Hb46Sl8-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 9b8addffa70cee5b2acc5454712d9cf78ce45710)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260204/202602041006.7Hb46Sl8-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202602041006.7Hb46Sl8-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/soc/hisilicon/hisi_soc_l3c.c:251:7: error: call to undeclared function 'alloc_contig_pages'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     251 |         pg = alloc_contig_pages(1 << order, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO,
         |              ^
>> drivers/soc/hisilicon/hisi_soc_l3c.c:251:5: error: incompatible integer to pointer conversion assigning to 'struct page *' from 'int' [-Wint-conversion]
     251 |         pg = alloc_contig_pages(1 << order, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO,
         |            ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     252 |                                 cpu_to_node(smp_processor_id()), NULL);
         |                                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   2 errors generated.


vim +/alloc_contig_pages +251 drivers/soc/hisilicon/hisi_soc_l3c.c

   237	
   238	static int hisi_l3c_mmap(struct file *file, struct vm_area_struct *vma)
   239	{
   240		unsigned long size = vma->vm_end - vma->vm_start;
   241		int order = get_order(size);
   242		unsigned long addr;
   243		struct page *pg;
   244		int ret;
   245	
   246		struct hisi_l3c_lock_region *clr __free(kfree) = kzalloc(sizeof(*clr), GFP_KERNEL);
   247		if (!clr)
   248			return -ENOMEM;
   249	
   250		/* Continuous physical memory is required for L3 cache lock. */
 > 251		pg = alloc_contig_pages(1 << order, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO,
   252					cpu_to_node(smp_processor_id()), NULL);
   253		if (!pg)
   254			return -ENOMEM;
   255	
   256		addr = page_to_phys(pg);
   257		*clr = (struct hisi_l3c_lock_region) {
   258			.addr = addr,
   259			.size = size,
   260			.cpu = smp_processor_id(),
   261			/* vma should not be moved, store here for validation */
   262			.vm_start = vma->vm_start,
   263			.vm_end = vma->vm_end,
   264		};
   265	
   266		vm_flags_set(vma, VM_DONTCOPY | VM_DONTEXPAND);
   267		vma->vm_ops = &hisi_l3c_vm_ops;
   268		vma->vm_private_data = clr;
   269	
   270		hisi_l3c_vm_ops.open(vma);
   271		if (clr->status) {
   272			ret = clr->status;
   273			goto out_page;
   274		}
   275	
   276		ret = remap_pfn_range(vma, vma->vm_start, PFN_DOWN(addr), size,
   277				      vma->vm_page_prot);
   278		if (ret)
   279			goto out_page;
   280	
   281		/* Save clr from being freed when lock succeeds. */
   282		vma->vm_private_data = no_free_ptr(clr);
   283	
   284		return 0;
   285	
   286	out_page:
   287		free_contig_range(PHYS_PFN(clr->addr), 1 << order);
   288		return ret;
   289	}
   290	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


  parent reply	other threads:[~2026-02-04  2:48 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-03 16:18 [PATCH 0/3] soc: Enable cache lockdown for HiSilicon L3 cache Yushan Wang
2026-02-03 16:18 ` [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC Yushan Wang
2026-02-03 17:19   ` Arnd Bergmann
2026-02-04  9:51     ` wangyushan
2026-02-05  9:37     ` Krzysztof Kozlowski
2026-02-05 11:19       ` wangyushan
2026-02-05 11:23         ` Krzysztof Kozlowski
2026-02-05 11:30           ` wangyushan
2026-02-04  0:10   ` Linus Walleij
2026-02-04  9:53     ` wangyushan
2026-02-04 10:06       ` Linus Walleij
2026-02-04 13:40     ` Jonathan Cameron
2026-02-04 13:44       ` Jonathan Cameron
2026-02-05  2:20         ` SeongJae Park
2026-02-05  9:12       ` Linus Walleij
2026-02-05 10:18         ` Jonathan Cameron
2026-02-05 13:47           ` Linus Walleij
2026-02-05 14:38             ` Arnd Bergmann
2026-02-06  8:05               ` Linus Walleij
2026-02-05 14:37           ` Ben Horgan
2026-02-06  9:54           ` wangyushan
2026-02-06 16:15             ` Ben Horgan
2026-02-06 10:07       ` wangyushan
2026-02-06 10:44         ` Arnd Bergmann
2026-02-06 12:44         ` Linus Walleij
2026-02-04  2:47   ` kernel test robot [this message]
2026-02-03 16:18 ` [PATCH 2/3] soc cache: L3 cache lockdown support " Yushan Wang
2026-02-03 16:18 ` [PATCH 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache Yushan Wang

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