Re: [PATCH v2 0/2] Performant CXL type 3 non-interleaved regions

[Jonathan Cameron via qemu development <qemu-devel@nongnu.org>]

On Sun, 8 Feb 2026 22:17:46 -0500
Gregory Price <gourry@gourry.net> wrote:

> On Wed, Feb 04, 2026 at 02:59:59PM +0000, Alireza Sanaee wrote:
> > The CXL address to device decoding logic is complex because of the need
> > to correctly decode fine grained interleave. The current implementation
> > prevents use with KVM where executed instructions may reside in that
> > memory and gives very slow performance even in TCG.
> > 
> > In many real cases non interleaved memory configurations are useful and
> > for those we can use a more conventional memory region alias allowing
> > similar performance to other memory in the system.
> > 
> > Whether this fast path is applicable can be established once the full
> > set of HDM decoders has been committed (in whatever order the guest
> > decides to commit them). As such a check is performed on each commit /
> > uncommit of HDM decoder to establish if the alias should be added or
> > removed.
> >   
> 
> Tested this on top of Jonathan's most recent draft branch, works nicely
> (with obvious fixups mentioned here). Has been working nicely.
> 
> Tested-by: Gregory Price <gourry@gourry.net>
> 
> 
> ----
> 
> Jonathan the HACK patch was giving me issues with registers getting
> plopped in the middle of a CFMW, not sure if this is the right fix or not
> 
> Fixes: 9a1b11bc03 hw/i386/pc: Add Aspeed i2c controller + MCTP with ACPI table

I'm kind of planning to drop the I2C / MCTP stuff anyway very soon as the
USB route is much less hacky and avoids need for hiding these registers somewhere.

I'll push a new draft branch soon (probably later this week) - Ideally that'll have
the DCD equivalent of this fast path as well.

The code definitely looks wrong.  If I keep the I2C stuff in my tree I'll
try and figure out what it should be doing...

Note if anyone sees this and really wants the I2C stuff then shout.
If not I'll drop it and see if anyone shouts ;)

Thanks!

Jonathan


> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index f9d0bb3b41..9c244d40a7 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -957,8 +957,8 @@ void pc_memory_init(PCMachineState *pcms,
>          memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
>          memory_region_add_subregion(system_memory, cxl_base, mr);
>          cxl_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
> -        pcms->i2c_base = cxl_base + cxl_size - 0x4000;

At first glance I thing this is misplaced and should be before the line
above that updates the cxl_base.  It's still a horrible hack as it
will be grabbing a bit of the host reg space and relying on their
not being so many host bridges that we run out of space and get an overlap
for that.

>          cxl_resv_end = cxl_fmws_set_memmap(cxl_base, maxphysaddr);
> +        pcms->i2c_base = cxl_resv_end + 0x1000;
>          cxl_fmws_update_mmio();
>      }
>