Re: [RFC] AMD VM crashing on deferred memory error injection

[Yazen Ghannam <yazen.ghannam@amd.com>]

On Mon, Feb 09, 2026 at 04:08:19PM -0500, Yazen Ghannam wrote:
> On Mon, Feb 09, 2026 at 05:36:32PM +0100, William Roche wrote:

[...]

> > According to me, this small kernel fix relies too much on a Qemu AMD
> > specific implementation detail.
> > 
> > Would you have a more appropriate fix to suggest please ?
> > 
> > Thanks in advance for your feedback.
> > William.
> 
> Thanks William for the report and details.
> 
> Clearing "STATUS" registers is a normal part of MCA handling.
> 
> We seem to allow clearing the regular "MCi_STATUS" register. I assume
> this gets trapped/ignored by the hypervisor.
> 
> I expect we need to do the same behavior for the "MCA_DESTAT" register.
> 
> I'll do some research here, but please do share any pointers you may
> have.

Sorry for the rapid reply, but I think this is where we need an update.

Linux:
arch/x86/kvm/x86.c : set_msr_mce()

Please note the comment:
"All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR."

We should include the MCA_DESTAT register range here.

What do you think?

Thanks,
Yazen