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From: Rob Herring <robh@kernel.org>
To: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Cc: Thomas Gleixner <tglx@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Huacai Chen <chenhuacai@kernel.org>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-mips@vger.kernel.org
Subject: Re: [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC
Date: Mon, 9 Feb 2026 17:48:18 -0600	[thread overview]
Message-ID: <20260209234818.GA2119841-robh@kernel.org> (raw)
In-Reply-To: <20260131094547.455916-3-zhengxingda@iscas.ac.cn>

On Sat, Jan 31, 2026 at 05:45:41PM +0800, Icenowy Zheng wrote:
> Loongson 7A series PCH contains an LPC controller with an interrupt
> controller.
> 
> Add the device tree binding for the interrupt controller.
> 
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
>  .../loongson,pch-lpc.yaml                     | 52 +++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> new file mode 100644
> index 0000000000000..c00fbf31f47f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson PCH LPC Controller
> +
> +maintainers:
> +  - Jiaxun Yang <jiaxun.yang@flygoat.com>
> +
> +description:
> +  This interrupt controller is found in the Loongson LS7A family of PCH for
> +  accepting interrupts sent by LPC-connected peripherals and signalling PIC
> +  via a single interrupt line when interrupts are available.
> +
> +properties:
> +  compatible:
> +    const: loongson,pch-lpc-1.0

Where does 1.0 come from? We don't do version numbers generally unless 
you define where the versions come from (e.g. Soft IP releases for 
FPGAs). I would have expected "ls7a" in the compatible instead.

Rob

  reply	other threads:[~2026-02-09 23:48 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-31  9:45 [PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems Icenowy Zheng
2026-01-31  9:45 ` [PATCH 1/8] genirq: reserve NR_IRQS_LEGACY IRQs in dynirq by default Icenowy Zheng
2026-01-31  9:45 ` [PATCH 2/8] dt-bindings: interrupt-controller: add LS7A PCH LPC Icenowy Zheng
2026-02-09 23:48   ` Rob Herring [this message]
2026-02-10  6:33     ` Icenowy Zheng
2026-02-10 10:51     ` Icenowy Zheng
2026-02-10 12:47       ` Huacai Chen
2026-01-31  9:45 ` [PATCH 3/8] irqchip/loongson-pch-lpc: extract non-ACPI-related code from ACPI init Icenowy Zheng
2026-01-31 14:05   ` kernel test robot
2026-02-01 16:15   ` Thomas Gleixner
2026-01-31  9:45 ` [PATCH 4/8] irqchip/loongson-pch-lpc: guard ACPI init code with CONFIG_ACPI Icenowy Zheng
2026-01-31  9:45 ` [PATCH 5/8] irqchip/loongson-pch-lpc: add OF init code Icenowy Zheng
2026-01-31 19:59   ` kernel test robot
2026-02-01  2:33   ` Huacai Chen
2026-02-01 16:17     ` Thomas Gleixner
2026-02-01 16:19   ` Thomas Gleixner
2026-02-02  5:50     ` Icenowy Zheng
2026-02-02  9:55       ` Thomas Gleixner
2026-02-02  1:12   ` kernel test robot
2026-01-31  9:45 ` [PATCH 6/8] irqchip/loongson-pch-lpc: enable building on MIPS Loongson64 Icenowy Zheng
2026-01-31  9:45 ` [PATCH 7/8] MIPS: Loongson64: dts: sort nodes Icenowy Zheng
2026-01-31  9:45 ` [PATCH 8/8] MIPS: Loongson64: dts: add node for LS7A PCH LPC Icenowy Zheng
2026-02-01  9:57 ` [PATCH 0/8] Add support for LS7A LPC IRQ for MIPS Loongson systems Yao Zi

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