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Tue, 10 Feb 2026 09:10:46 +0000 From: Jamin Lin To: Paolo Bonzini , Peter Maydell , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , =?iso-8859-1?Q?Marc-Andr=E9_Lureau?= , =?iso-8859-1?Q?Daniel_P=2E_Berrang=E9?= , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= , "open list:All patches CC here" , "open list:ARM TCG CPUs" CC: Jamin Lin , Troy Lee , Kane Chen , "nabihestefan@google.com" , Joe Komlodi , Titus Rwantare , Patrick Venture Subject: [PATCH v5 18/21] hw/i3c: Add Mock target Thread-Topic: [PATCH v5 18/21] hw/i3c: Add Mock target Thread-Index: AQHcmm0kEufGdnpVB0yRA+lK+teccg== Date: Tue, 10 Feb 2026 09:10:46 +0000 Message-ID: <20260210091018.1553489-19-jamin_lin@aspeedtech.com> References: <20260210091018.1553489-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260210091018.1553489-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYPPR06MB8206.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 56b3074b-9bf8-433d-b191-08de688446a6 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Feb 2026 09:10:46.2976 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: i+nfbjOfc87Ir0Jbziha/m6kkRhPBVbwEo/nT2qRZd7L7maSmCsbXIs5MyMbNfEb65zfarJFjGTaumO6o2IED4RnyL/yF1LcvQ2ZW+A2BDk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUZPR06MB8268 Received-SPF: pass client-ip=2a01:111:f403:c40f::6; envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Adds a simple i3c device to be used for testing in lieu of a real=0A= device.=0A= =0A= The mock target supports the following features:=0A= - A buffer that users can read and write to.=0A= - CCC support for commonly used CCCs when probing devices on an I3C bus.=0A= - IBI sending upon receiving a user-defined byte.=0A= =0A= Signed-off-by: Joe Komlodi =0A= Reviewed-by: Titus Rwantare =0A= Reviewed-by: Patrick Venture =0A= Reviewed-by: Jamin Lin =0A= Signed-off-by: Jamin Lin =0A= ---=0A= include/hw/i3c/mock-i3c-target.h | 52 ++++++=0A= hw/i3c/mock-i3c-target.c | 298 +++++++++++++++++++++++++++++++=0A= hw/i3c/Kconfig | 10 ++=0A= hw/i3c/meson.build | 1 +=0A= hw/i3c/trace-events | 10 ++=0A= 5 files changed, 371 insertions(+)=0A= create mode 100644 include/hw/i3c/mock-i3c-target.h=0A= create mode 100644 hw/i3c/mock-i3c-target.c=0A= =0A= diff --git a/include/hw/i3c/mock-i3c-target.h b/include/hw/i3c/mock-i3c-tar= get.h=0A= new file mode 100644=0A= index 0000000000..8c6003ae8b=0A= --- /dev/null=0A= +++ b/include/hw/i3c/mock-i3c-target.h=0A= @@ -0,0 +1,52 @@=0A= +#ifndef MOCK_I3C_TARGET_H_=0A= +#define MOCK_I3C_TARGET_H_=0A= +=0A= +/*=0A= + * Mock I3C Device=0A= + *=0A= + * Copyright (c) 2025 Google LLC=0A= + *=0A= + * The mock I3C device can be thought of as a simple EEPROM. It has a buff= er,=0A= + * and the pointer in the buffer is reset to 0 on an I3C STOP.=0A= + * To write to the buffer, issue a private write and send data.=0A= + * To read from the buffer, issue a private read.=0A= + *=0A= + * The mock target also supports sending target interrupt IBIs.=0A= + * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number,= and=0A= + * send that number in a private transaction. The mock target will issue a= n IBI=0A= + * after 1 second.=0A= + *=0A= + * It also supports a handful of CCCs that are typically used when probing= I3C=0A= + * devices.=0A= + *=0A= + * SPDX-License-Identifier: GPL-2.0-or-later=0A= + */=0A= +=0A= +#include "qemu/osdep.h"=0A= +#include "qemu/timer.h"=0A= +#include "hw/i3c/i3c.h"=0A= +=0A= +#define TYPE_MOCK_I3C_TARGET "mock-i3c-target"=0A= +OBJECT_DECLARE_SIMPLE_TYPE(MockI3cTargetState, MOCK_I3C_TARGET)=0A= +=0A= +struct MockI3cTargetState {=0A= + I3CTarget parent_obj;=0A= +=0A= + /* General device state */=0A= + bool can_ibi;=0A= + QEMUTimer qtimer;=0A= + size_t p_buf;=0A= + uint8_t *buf;=0A= +=0A= + /* For Handing CCCs. */=0A= + bool in_ccc;=0A= + I3CCCC curr_ccc;=0A= + uint8_t ccc_byte_offset;=0A= +=0A= + struct {=0A= + uint32_t buf_size;=0A= + uint8_t ibi_magic;=0A= + } cfg;=0A= +};=0A= +=0A= +#endif=0A= diff --git a/hw/i3c/mock-i3c-target.c b/hw/i3c/mock-i3c-target.c=0A= new file mode 100644=0A= index 0000000000..875cd7c7d0=0A= --- /dev/null=0A= +++ b/hw/i3c/mock-i3c-target.c=0A= @@ -0,0 +1,298 @@=0A= +/*=0A= + * Mock I3C Device=0A= + *=0A= + * Copyright (c) 2025 Google LLC=0A= + *=0A= + * The mock I3C device can be thought of as a simple EEPROM. It has a buff= er,=0A= + * and the pointer in the buffer is reset to 0 on an I3C STOP.=0A= + * To write to the buffer, issue a private write and send data.=0A= + * To read from the buffer, issue a private read.=0A= + *=0A= + * The mock target also supports sending target interrupt IBIs.=0A= + * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number,= and=0A= + * send that number in a private transaction. The mock target will issue a= n IBI=0A= + * after 1 second.=0A= + *=0A= + * It also supports a handful of CCCs that are typically used when probing= I3C=0A= + * devices.=0A= + *=0A= + * SPDX-License-Identifier: GPL-2.0-or-later=0A= + */=0A= +=0A= +#include "qemu/osdep.h"=0A= +#include "qemu/log.h"=0A= +#include "trace.h"=0A= +#include "hw/i3c/i3c.h"=0A= +#include "hw/i3c/mock-i3c-target.h"=0A= +#include "hw/core/irq.h"=0A= +#include "hw/core/qdev-properties.h"=0A= +#include "qapi/error.h"=0A= +#include "qemu/module.h"=0A= +=0A= +#define IBI_DELAY_NS (1 * 1000 * 1000)=0A= +=0A= +static uint32_t mock_i3c_target_rx(I3CTarget *i3c, uint8_t *data,=0A= + uint32_t num_to_read)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c);=0A= + uint32_t i;=0A= +=0A= + /* Bounds check. */=0A= + if (s->p_buf =3D=3D s->cfg.buf_size) {=0A= + return 0;=0A= + }=0A= +=0A= + for (i =3D 0; i < num_to_read; i++) {=0A= + data[i] =3D s->buf[s->p_buf];=0A= + trace_mock_i3c_target_rx(data[i]);=0A= + s->p_buf++;=0A= + if (s->p_buf =3D=3D s->cfg.buf_size) {=0A= + break;=0A= + }=0A= + }=0A= +=0A= + /* Return the number of bytes we're sending to the controller. */=0A= + return i;=0A= +}=0A= +=0A= +static void mock_i3c_target_ibi_timer_start(MockI3cTargetState *s)=0A= +{=0A= + int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);=0A= + timer_mod(&s->qtimer, now + IBI_DELAY_NS);=0A= +}=0A= +=0A= +static int mock_i3c_target_tx(I3CTarget *i3c, const uint8_t *data,=0A= + uint32_t num_to_send, uint32_t *num_sent)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c);=0A= + int ret;=0A= + uint32_t to_write;=0A= +=0A= + if (s->cfg.ibi_magic && num_to_send =3D=3D 1 && s->cfg.ibi_magic =3D= =3D *data) {=0A= + mock_i3c_target_ibi_timer_start(s);=0A= + return 0;=0A= + }=0A= +=0A= + /* Bounds check. */=0A= + if (num_to_send + s->p_buf > s->cfg.buf_size) {=0A= + to_write =3D s->cfg.buf_size - s->p_buf;=0A= + ret =3D -1;=0A= + } else {=0A= + to_write =3D num_to_send;=0A= + ret =3D 0;=0A= + }=0A= + for (uint32_t i =3D 0; i < to_write; i++) {=0A= + trace_mock_i3c_target_tx(data[i]);=0A= + s->buf[s->p_buf] =3D data[i];=0A= + s->p_buf++;=0A= + }=0A= + return ret;=0A= +}=0A= +=0A= +static int mock_i3c_target_event(I3CTarget *i3c, enum I3CEvent event)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c);=0A= +=0A= + trace_mock_i3c_target_event(event);=0A= + if (event =3D=3D I3C_STOP) {=0A= + s->in_ccc =3D false;=0A= + s->curr_ccc =3D 0;=0A= + s->ccc_byte_offset =3D 0;=0A= + s->p_buf =3D 0;=0A= + }=0A= +=0A= + return 0;=0A= +}=0A= +=0A= +static int mock_i3c_target_handle_ccc_read(I3CTarget *i3c, uint8_t *data,= =0A= + uint32_t num_to_read,=0A= + uint32_t *num_read)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c);=0A= +=0A= + switch (s->curr_ccc) {=0A= + case I3C_CCCD_GETMXDS:=0A= + /* Default data rate for I3C. */=0A= + while (s->ccc_byte_offset < num_to_read) {=0A= + if (s->ccc_byte_offset >=3D 2) {=0A= + break;=0A= + }=0A= + data[s->ccc_byte_offset] =3D 0;=0A= + *num_read =3D s->ccc_byte_offset;=0A= + s->ccc_byte_offset++;=0A= + }=0A= + break;=0A= + case I3C_CCCD_GETCAPS:=0A= + /* Support I3C version 1.1.x, no other features. */=0A= + while (s->ccc_byte_offset < num_to_read) {=0A= + if (s->ccc_byte_offset >=3D 2) {=0A= + break;=0A= + }=0A= + if (s->ccc_byte_offset =3D=3D 0) {=0A= + data[s->ccc_byte_offset] =3D 0;=0A= + } else {=0A= + data[s->ccc_byte_offset] =3D 0x01;=0A= + }=0A= + *num_read =3D s->ccc_byte_offset;=0A= + s->ccc_byte_offset++;=0A= + }=0A= + break;=0A= + case I3C_CCCD_GETMWL:=0A= + case I3C_CCCD_GETMRL:=0A= + /* MWL/MRL is MSB first. */=0A= + while (s->ccc_byte_offset < num_to_read) {=0A= + if (s->ccc_byte_offset >=3D 2) {=0A= + break;=0A= + }=0A= + data[s->ccc_byte_offset] =3D (s->cfg.buf_size &=0A= + (0xff00 >> (s->ccc_byte_offset * 8= ))) >>=0A= + (8 - (s->ccc_byte_offset * 8));=0A= + s->ccc_byte_offset++;=0A= + *num_read =3D num_to_read;=0A= + }=0A= + break;=0A= + case I3C_CCC_ENTDAA:=0A= + case I3C_CCCD_GETPID:=0A= + case I3C_CCCD_GETBCR:=0A= + case I3C_CCCD_GETDCR:=0A= + /* Nothing to do. */=0A= + break;=0A= + default:=0A= + qemu_log_mask(LOG_GUEST_ERROR, "Unhandled CCC 0x%.2x\n", s->curr_c= cc);=0A= + return -1;=0A= + }=0A= +=0A= + trace_mock_i3c_target_handle_ccc_read(*num_read, num_to_read);=0A= + return 0;=0A= +}=0A= +=0A= +static int mock_i3c_target_handle_ccc_write(I3CTarget *i3c, const uint8_t = *data,=0A= + uint32_t num_to_send,=0A= + uint32_t *num_sent)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c);=0A= +=0A= + if (!s->curr_ccc) {=0A= + s->in_ccc =3D true;=0A= + s->curr_ccc =3D *data;=0A= + trace_mock_i3c_target_new_ccc(s->curr_ccc);=0A= + }=0A= +=0A= + *num_sent =3D 1;=0A= + switch (s->curr_ccc) {=0A= + case I3C_CCC_ENEC:=0A= + case I3C_CCCD_ENEC:=0A= + s->can_ibi =3D true;=0A= + break;=0A= + case I3C_CCC_DISEC:=0A= + case I3C_CCCD_DISEC:=0A= + s->can_ibi =3D false;=0A= + break;=0A= + case I3C_CCC_ENTDAA:=0A= + case I3C_CCC_SETAASA:=0A= + case I3C_CCC_RSTDAA:=0A= + case I3C_CCCD_SETDASA:=0A= + case I3C_CCCD_GETPID:=0A= + case I3C_CCCD_GETBCR:=0A= + case I3C_CCCD_GETDCR:=0A= + case I3C_CCCD_GETMWL:=0A= + case I3C_CCCD_GETMRL:=0A= + case I3C_CCCD_GETMXDS:=0A= + case I3C_CCCD_GETCAPS:=0A= + /* Nothing to do. */=0A= + break;=0A= + default:=0A= + qemu_log_mask(LOG_GUEST_ERROR, "Unhandled CCC 0x%.2x\n", s->curr_c= cc);=0A= + return -1;=0A= + }=0A= +=0A= + trace_mock_i3c_target_handle_ccc_write(*num_sent, num_to_send);=0A= + return 0;=0A= +}=0A= +=0A= +static void mock_i3c_target_do_ibi(MockI3cTargetState *s)=0A= +{=0A= + if (!s->can_ibi) {=0A= + return;=0A= + }=0A= +=0A= + trace_mock_i3c_target_do_ibi(s->parent_obj.address, true);=0A= + int nack =3D i3c_target_send_ibi(&s->parent_obj, s->parent_obj.address= ,=0A= + /*is_recv=3D*/true);=0A= + /* Getting NACKed isn't necessarily an error, just print it out. */=0A= + if (nack) {=0A= + trace_mock_i3c_target_do_ibi_nack("sending");=0A= + }=0A= + nack =3D i3c_target_ibi_finish(&s->parent_obj, 0x00);=0A= + if (nack) {=0A= + trace_mock_i3c_target_do_ibi_nack("finishing");=0A= + }=0A= +}=0A= +=0A= +static void mock_i3c_target_timer_elapsed(void *opaque)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(opaque);=0A= + timer_del(&s->qtimer);=0A= + mock_i3c_target_do_ibi(s);=0A= +}=0A= +=0A= +static void mock_i3c_target_reset(I3CTarget *i3c)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c);=0A= + s->can_ibi =3D false;=0A= +}=0A= +=0A= +static void mock_i3c_target_realize(DeviceState *dev, Error **errp)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(dev);=0A= + s->buf =3D g_new0(uint8_t, s->cfg.buf_size);=0A= + mock_i3c_target_reset(&s->parent_obj);=0A= +}=0A= +=0A= +static void mock_i3c_target_init(Object *obj)=0A= +{=0A= + MockI3cTargetState *s =3D MOCK_I3C_TARGET(obj);=0A= + s->can_ibi =3D false;=0A= +=0A= + /* For IBIs. */=0A= + timer_init_ns(&s->qtimer, QEMU_CLOCK_VIRTUAL, mock_i3c_target_timer_el= apsed,=0A= + s);=0A= +}=0A= +=0A= +static const Property remote_i3c_props[] =3D {=0A= + /* The size of the internal buffer. */=0A= + DEFINE_PROP_UINT32("buf-size", MockI3cTargetState, cfg.buf_size, 0x100= ),=0A= + /*=0A= + * If the mock target receives this number, it will issue an IBI after= =0A= + * 1 second. Disabled if the IBI magic number is 0.=0A= + */=0A= + DEFINE_PROP_UINT8("ibi-magic-num", MockI3cTargetState, cfg.ibi_magic, = 0x00),=0A= +};=0A= +=0A= +static void mock_i3c_target_class_init(ObjectClass *klass, const void *dat= a)=0A= +{=0A= + DeviceClass *dc =3D DEVICE_CLASS(klass);=0A= + I3CTargetClass *k =3D I3C_TARGET_CLASS(klass);=0A= +=0A= + dc->realize =3D mock_i3c_target_realize;=0A= + k->event =3D mock_i3c_target_event;=0A= + k->recv =3D mock_i3c_target_rx;=0A= + k->send =3D mock_i3c_target_tx;=0A= + k->handle_ccc_read =3D mock_i3c_target_handle_ccc_read;=0A= + k->handle_ccc_write =3D mock_i3c_target_handle_ccc_write;=0A= +=0A= + device_class_set_props(dc, remote_i3c_props);=0A= +}=0A= +=0A= +static const TypeInfo mock_i3c_target_types[] =3D {=0A= + {=0A= + .name =3D TYPE_MOCK_I3C_TARGET,=0A= + .parent =3D TYPE_I3C_TARGET,=0A= + .instance_size =3D sizeof(MockI3cTargetState),=0A= + .instance_init =3D mock_i3c_target_init,=0A= + .class_init =3D mock_i3c_target_class_init,=0A= + },=0A= +};=0A= +=0A= +DEFINE_TYPES(mock_i3c_target_types)=0A= +=0A= diff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig=0A= index ecec77d6fc..d5c6d4049b 100644=0A= --- a/hw/i3c/Kconfig=0A= +++ b/hw/i3c/Kconfig=0A= @@ -3,3 +3,13 @@ config I3C=0A= =0A= config DW_I3C=0A= bool=0A= +=0A= +config I3C_DEVICES=0A= + # Device group for i3c devices which can reasonably be user-plugged to= any=0A= + # board's i3c bus.=0A= + bool=0A= +=0A= +config MOCK_I3C_TARGET=0A= + bool=0A= + select I3C=0A= + default y if I3C_DEVICES=0A= diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build=0A= index 83d75e7d5c..e614b18712 100644=0A= --- a/hw/i3c/meson.build=0A= +++ b/hw/i3c/meson.build=0A= @@ -2,4 +2,5 @@ i3c_ss =3D ss.source_set()=0A= i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c'))=0A= i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c'))=0A= i3c_ss.add(when: 'CONFIG_DW_I3C', if_true: files('dw-i3c.c'))=0A= +i3c_ss.add(when: 'CONFIG_MOCK_I3C_TARGET', if_true: files('mock-i3c-target= .c'))=0A= system_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss)=0A= diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events=0A= index 39f33d9a50..9e58edec99 100644=0A= --- a/hw/i3c/trace-events=0A= +++ b/hw/i3c/trace-events=0A= @@ -36,3 +36,13 @@ legacy_i2c_recv(uint8_t byte) "Legacy I2C recv 0x%" PRIx= 8=0A= legacy_i2c_send(uint8_t byte) "Legacy I2C send 0x%" PRIx8=0A= legacy_i2c_start_transfer(uint8_t address, bool is_recv) "Legacy I2C START= with address 0x%" PRIx8 " is_recv=3D%d"=0A= legacy_i2c_end_transfer(void) "Legacy I2C STOP"=0A= +=0A= +# mock-target.c=0A= +mock_i3c_target_rx(uint8_t byte) "I3C mock target read 0x%" PRIx8=0A= +mock_i3c_target_tx(uint8_t byte) "I3C mock target write 0x%" PRIx8=0A= +mock_i3c_target_event(uint8_t event) "I3C mock target event 0x%" PRIx8=0A= +mock_i3c_target_handle_ccc_read(uint32_t num_read, uint32_t num_to_read) "= I3C mock target read %" PRId32 "/%" PRId32 " bytes"=0A= +mock_i3c_target_new_ccc(uint8_t ccc) "I3C mock target handle CCC 0x%" PRIx= 8=0A= +mock_i3c_target_handle_ccc_write(uint32_t num_sent, uint32_t num_to_send) = "I3C mock target send %" PRId32 "/%" PRId32 " bytes"=0A= +mock_i3c_target_do_ibi(uint8_t address, bool is_recv) "I3C mock target IBI= with address 0x%" PRIx8 " RnW=3D%d"=0A= +mock_i3c_target_do_ibi_nack(const char *reason) "NACKed from controller wh= en %s target interrupt"=0A= -- =0A= 2.43.0=0A=