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=?iso-8859-1?Q?Marc-Andr=E9_Lureau?= , =?iso-8859-1?Q?Daniel_P=2E_Berrang=E9?= , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= , "open list:All patches CC here" , "open list:ARM TCG CPUs" CC: Jamin Lin , Troy Lee , Kane Chen , "nabihestefan@google.com" , Joe Komlodi , Patrick Venture Subject: [PATCH v5 05/21] hw/i3c/dw-i3c: Add more register fields Thread-Topic: [PATCH v5 05/21] hw/i3c/dw-i3c: Add more register fields Thread-Index: AQHcmm0YgPZlS9q25EqHG1SjEZnJsg== Date: Tue, 10 Feb 2026 09:10:27 +0000 Message-ID: <20260210091018.1553489-6-jamin_lin@aspeedtech.com> References: <20260210091018.1553489-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260210091018.1553489-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: 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VaDWyhLe08o4k1XxuJmJ1SWa4bW++AyVKIl51QdrIgfj9Lme2XBwsWKy2A6XwFZ9Tt181h4pqkIj15V5lIKS7yWu5rbVVEpjAP0+0AC8pgA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUZPR06MB8268 Received-SPF: pass client-ip=2a01:111:f403:c406::3; envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_75_100=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Adds the rest of the Designware register fields.=0A= =0A= Signed-off-by: Joe Komlodi =0A= Reviewed-by: Patrick Venture =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/i3c/dw-i3c.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++++=0A= 1 file changed, 199 insertions(+)=0A= =0A= diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c=0A= index 6cadc59191..48dde008de 100644=0A= --- a/hw/i3c/dw-i3c.c=0A= +++ b/hw/i3c/dw-i3c.c=0A= @@ -19,54 +19,253 @@=0A= #include "trace.h"=0A= =0A= REG32(DEVICE_CTRL, 0x00)=0A= + FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1)=0A= + FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1)=0A= + FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1)=0A= + FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2)=0A= + FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1)=0A= + FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1)=0A= + FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1)=0A= + FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1)=0A= + FIELD(DEVICE_CTRL, I3C_EN, 31, 1)=0A= REG32(DEVICE_ADDR, 0x04)=0A= + FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7)=0A= + FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1)=0A= + FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7)=0A= + FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 31, 1)=0A= REG32(HW_CAPABILITY, 0x08)=0A= + FIELD(HW_CAPABILITY, DEVICE_ROLE_CONFIG, 0, 3)=0A= + FIELD(HW_CAPABILITY, HDR_DDR, 3, 1)=0A= + FIELD(HW_CAPABILITY, HDR_TS, 4, 1)=0A= REG32(COMMAND_QUEUE_PORT, 0x0c)=0A= + FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3)=0A= + /* Transfer command structure */=0A= + FIELD(COMMAND_QUEUE_PORT, TID, 3, 4)=0A= + FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8)=0A= + FIELD(COMMAND_QUEUE_PORT, CP, 15, 1)=0A= + FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5)=0A= + FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3)=0A= + FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1)=0A= + FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1)=0A= + FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1)=0A= + FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1)=0A= + FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1)=0A= + /* Transfer argument data structure */=0A= + FIELD(COMMAND_QUEUE_PORT, DB, 8, 8)=0A= + FIELD(COMMAND_QUEUE_PORT, DL, 16, 16)=0A= + /* Short data argument data structure */=0A= + FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3)=0A= + FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8)=0A= + FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8)=0A= + FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8)=0A= + /* Address assignment command structure */=0A= + /*=0A= + * bits 3..21 and 26..31 are the same as the transfer command structur= e, or=0A= + * marked as reserved.=0A= + */=0A= + FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3)=0A= REG32(RESPONSE_QUEUE_PORT, 0x10)=0A= + FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16)=0A= + FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8)=0A= + FIELD(RESPONSE_QUEUE_PORT, TID, 24, 3)=0A= + FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4)=0A= REG32(RX_TX_DATA_PORT, 0x14)=0A= REG32(IBI_QUEUE_STATUS, 0x18)=0A= + FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8)=0A= + FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8)=0A= + FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1)=0A= + FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1)=0A= + FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1)=0A= REG32(IBI_QUEUE_DATA, 0x18)=0A= REG32(QUEUE_THLD_CTRL, 0x1c)=0A= + FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8);=0A= + FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8);=0A= + FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 5);=0A= + FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8);=0A= REG32(DATA_BUFFER_THLD_CTRL, 0x20)=0A= + FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3)=0A= + FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 8, 3)=0A= + FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3)=0A= + FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3)=0A= REG32(IBI_QUEUE_CTRL, 0x24)=0A= + FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1)=0A= + FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1)=0A= + FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1)=0A= REG32(IBI_MR_REQ_REJECT, 0x2c)=0A= REG32(IBI_SIR_REQ_REJECT, 0x30)=0A= REG32(RESET_CTRL, 0x34)=0A= + FIELD(RESET_CTRL, CORE_RESET, 0, 1)=0A= + FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1)=0A= + FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1)=0A= + FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1)=0A= + FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1)=0A= + FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1)=0A= REG32(SLV_EVENT_CTRL, 0x38)=0A= + FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1)=0A= + FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1)=0A= + FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1)=0A= + FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2)=0A= + FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1)=0A= + FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1)=0A= REG32(INTR_STATUS, 0x3c)=0A= + FIELD(INTR_STATUS, TX_THLD, 0, 1)=0A= + FIELD(INTR_STATUS, RX_THLD, 1, 1)=0A= + FIELD(INTR_STATUS, IBI_THLD, 2, 1)=0A= + FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1)=0A= + FIELD(INTR_STATUS, RESP_RDY, 4, 1)=0A= + FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1)=0A= + FIELD(INTR_STATUS, CCC_UPDATED, 6, 1)=0A= + FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1)=0A= + FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1)=0A= + FIELD(INTR_STATUS, DEFSLV, 10, 1)=0A= + FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1)=0A= + FIELD(INTR_STATUS, IBI_UPDATED, 12, 1)=0A= + FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1)=0A= REG32(INTR_STATUS_EN, 0x40)=0A= + FIELD(INTR_STATUS_EN, TX_THLD, 0, 1)=0A= + FIELD(INTR_STATUS_EN, RX_THLD, 1, 1)=0A= + FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1)=0A= + FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1)=0A= + FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1)=0A= + FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1)=0A= + FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1)=0A= + FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1)=0A= + FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1)=0A= + FIELD(INTR_STATUS_EN, DEFSLV, 10, 1)=0A= + FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1)=0A= + FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1)=0A= + FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1)=0A= REG32(INTR_SIGNAL_EN, 0x44)=0A= + FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1)=0A= + FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1)=0A= + FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1)=0A= + FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1)=0A= + FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1)=0A= + FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1)=0A= + FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1)=0A= + FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1)=0A= + FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1)=0A= + FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1)=0A= + FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1)=0A= + FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1)=0A= + FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1)=0A= REG32(INTR_FORCE, 0x48)=0A= + FIELD(INTR_FORCE, TX_THLD, 0, 1)=0A= + FIELD(INTR_FORCE, RX_THLD, 1, 1)=0A= + FIELD(INTR_FORCE, IBI_THLD, 2, 1)=0A= + FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1)=0A= + FIELD(INTR_FORCE, RESP_RDY, 4, 1)=0A= + FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1)=0A= + FIELD(INTR_FORCE, CCC_UPDATED, 6, 1)=0A= + FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1)=0A= + FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1)=0A= + FIELD(INTR_FORCE, DEFSLV, 10, 1)=0A= + FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1)=0A= + FIELD(INTR_FORCE, IBI_UPDATED, 12, 1)=0A= + FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1)=0A= REG32(QUEUE_STATUS_LEVEL, 0x4c)=0A= + FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8)=0A= + FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8)=0A= + FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8)=0A= + FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5)=0A= REG32(DATA_BUFFER_STATUS_LEVEL, 0x50)=0A= + FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8)=0A= + FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8)=0A= REG32(PRESENT_STATE, 0x54)=0A= + FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1)=0A= + FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1)=0A= + FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1)=0A= + FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6)=0A= + FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6)=0A= + FIELD(PRESENT_STATE, CMD_TID, 24, 4)=0A= REG32(CCC_DEVICE_STATUS, 0x58)=0A= + FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4)=0A= + FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 5, 1)=0A= + FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2)=0A= + FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1)=0A= + FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1)=0A= + FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1)=0A= + FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1)=0A= + FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1)=0A= REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c)=0A= FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16)=0A= FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16)=0A= REG32(DEV_CHAR_TABLE_POINTER, 0x60)=0A= + FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12)=0A= + FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7)=0A= + FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3)=0A= REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c)=0A= + FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16)=0A= REG32(SLV_MIPI_PID_VALUE, 0x70)=0A= REG32(SLV_PID_VALUE, 0x74)=0A= + FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12)=0A= + FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4)=0A= + FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16)=0A= REG32(SLV_CHAR_CTRL, 0x78)=0A= + FIELD(SLV_CHAR_CTRL, BCR, 0, 8)=0A= + FIELD(SLV_CHAR_CTRL, DCR, 8, 8)=0A= + FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8)=0A= REG32(SLV_MAX_LEN, 0x7c)=0A= + FIELD(SLV_MAX_LEN, MWL, 0, 16)=0A= + FIELD(SLV_MAX_LEN, MRL, 16, 16)=0A= REG32(MAX_READ_TURNAROUND, 0x80)=0A= REG32(MAX_DATA_SPEED, 0x84)=0A= REG32(SLV_DEBUG_STATUS, 0x88)=0A= REG32(SLV_INTR_REQ, 0x8c)=0A= + FIELD(SLV_INTR_REQ, SIR, 0, 1)=0A= + FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2)=0A= + FIELD(SLV_INTR_REQ, MIR, 3, 1)=0A= + FIELD(SLV_INTR_REQ, TS, 4, 1)=0A= + FIELD(SLV_INTR_REQ, IBI_STS, 8, 2)=0A= +REG32(SLV_TSX_SYMBL_TIMING, 0x90)=0A= + FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6)=0A= REG32(DEVICE_CTRL_EXTENDED, 0xb0)=0A= + FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2)=0A= + FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1)=0A= REG32(SCL_I3C_OD_TIMING, 0xb4)=0A= + FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8)=0A= + FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8)=0A= REG32(SCL_I3C_PP_TIMING, 0xb8)=0A= + FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8)=0A= + FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8)=0A= REG32(SCL_I2C_FM_TIMING, 0xbc)=0A= REG32(SCL_I2C_FMP_TIMING, 0xc0)=0A= + FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16)=0A= + FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8)=0A= REG32(SCL_EXT_LCNT_TIMING, 0xc8)=0A= REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc)=0A= REG32(BUS_FREE_TIMING, 0xd4)=0A= REG32(BUS_IDLE_TIMING, 0xd8)=0A= + FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20)=0A= REG32(I3C_VER_ID, 0xe0)=0A= REG32(I3C_VER_TYPE, 0xe4)=0A= REG32(EXTENDED_CAPABILITY, 0xe8)=0A= REG32(SLAVE_CONFIG, 0xec)=0A= +/* Device characteristic table fields */=0A= +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200)=0A= +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200)=0A= + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8)= =0A= + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8)=0A= + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8)=0A= + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8)= =0A= +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204)=0A= + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16)=0A= +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208)=0A= + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8)=0A= + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8)=0A= +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c)=0A= + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8)=0A= +/* Dev addr table fields */=0A= +REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2)=0A= + FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)=0A= =0A= static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] =3D {=0A= [R_HW_CAPABILITY] =3D 0x000e00bf,=0A= -- =0A= 2.43.0=0A=