[PATCH v13 1/3] dt-bindings: clock: eswin: Documentation for eic7700 SoC

[dongxuyang@eswincomputing.com]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

Add device tree binding documentation for the ESWIN eic7700
clock controller module.

Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Troy Mitchell <troy.mitchell@linux.dev>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 .../bindings/clock/eswin,eic7700-clock.yaml   |  46 +++
 .../dt-bindings/clock/eswin,eic7700-clock.h   | 285 ++++++++++++++++++
 2 files changed, 331 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
 create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h

diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
new file mode 100644
index 000000000000..3125ae52bde6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC clock controller
+
+maintainers:
+  - Yifeng Huang <huangyifeng@eswincomputing.com>
+  - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description:
+  The clock controller generates and supplies clock to all the modules
+  for eic7700 SoC.
+
+properties:
+  compatible:
+    const: eswin,eic7700-clock
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: External 24MHz oscillator clock
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@51828000 {
+        compatible = "eswin,eic7700-clock";
+        reg = <0x51828000 0x300>;
+        clocks = <&xtal24m>;
+        #clock-cells = <1>;
+    };
diff --git a/include/dt-bindings/clock/eswin,eic7700-clock.h b/include/dt-bindings/clock/eswin,eic7700-clock.h
new file mode 100644
index 000000000000..d7ef697d0f7a
--- /dev/null
+++ b/include/dt-bindings/clock/eswin,eic7700-clock.h
@@ -0,0 +1,285 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 clock controller.
+ *
+ * Authors:
+ *	Yifeng Huang <huangyifeng@eswincomputing.com>
+ *	Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+
+#define EIC7700_CLK_XTAL_32K				0
+#define EIC7700_CLK_PLL_CPU				1
+#define EIC7700_CLK_SPLL0_FOUT1				2
+#define EIC7700_CLK_SPLL0_FOUT2				3
+#define EIC7700_CLK_SPLL0_FOUT3				4
+#define EIC7700_CLK_SPLL1_FOUT1				5
+#define EIC7700_CLK_SPLL1_FOUT2				6
+#define EIC7700_CLK_SPLL1_FOUT3				7
+#define EIC7700_CLK_SPLL2_FOUT1				8
+#define EIC7700_CLK_SPLL2_FOUT2				9
+#define EIC7700_CLK_SPLL2_FOUT3				10
+#define EIC7700_CLK_VPLL_FOUT1				11
+#define EIC7700_CLK_VPLL_FOUT2				12
+#define EIC7700_CLK_VPLL_FOUT3				13
+#define EIC7700_CLK_APLL_FOUT1				14
+#define EIC7700_CLK_APLL_FOUT2				15
+#define EIC7700_CLK_APLL_FOUT3				16
+#define EIC7700_CLK_EXT_MCLK				17
+#define EIC7700_CLK_LPDDR_REF_BAK			18
+#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE		19
+#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE		20
+#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE	21
+#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE	22
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0		23
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1		24
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2		25
+#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE		26
+#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE		27
+#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE	28
+#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE		29
+#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE	30
+#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE	31
+#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1		32
+#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE		33
+#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE		34
+#define EIC7700_CLK_MUX_SATA_PHY_2MUX1			35
+#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE		36
+#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE	37
+#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE	38
+#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK		39
+#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE	40
+#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE		41
+#define EIC7700_CLK_MUX_RMII_REF_2MUX			42
+#define EIC7700_CLK_MUX_ETH_CORE_2MUX1			43
+#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1		44
+#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE		45
+#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE	46
+#define EIC7700_CLK_DIV_SYS_CFG_DYNM			47
+#define EIC7700_CLK_DIV_NOC_NSP_DYNM			48
+#define EIC7700_CLK_DIV_BOOTSPI_DYNM			49
+#define EIC7700_CLK_DIV_SCPU_CORE_DYNM			50
+#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM			51
+#define EIC7700_CLK_DIV_GPU_ACLK_DYNM			52
+#define EIC7700_CLK_DIV_DSP_ACLK_DYNM			53
+#define EIC7700_CLK_DIV_D2D_ACLK_DYNM			54
+#define EIC7700_CLK_DIV_HSP_ACLK_DYNM			55
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0		56
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1		57
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0		58
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1		59
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2		60
+#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM			61
+#define EIC7700_CLK_DIV_NPU_ACLK_DYNM			62
+#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM		63
+#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM		64
+#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM		65
+#define EIC7700_CLK_DIV_VI_ACLK_DYNM			66
+#define EIC7700_CLK_DIV_VI_DVP_DYNM			67
+#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM			68
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0		69
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1		70
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2		71
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3		72
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4		73
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5		74
+#define EIC7700_CLK_DIV_VO_ACLK_DYNM			75
+#define EIC7700_CLK_DIV_IESMCLK_DYNM			76
+#define EIC7700_CLK_DIV_VO_PIXEL_DYNM			77
+#define EIC7700_CLK_DIV_VO_MCLK_DYNM			78
+#define EIC7700_CLK_DIV_VC_ACLK_DYNM			79
+#define EIC7700_CLK_DIV_JD_DYNM				80
+#define EIC7700_CLK_DIV_JE_DYNM				81
+#define EIC7700_CLK_DIV_VE_DYNM				82
+#define EIC7700_CLK_DIV_VD_DYNM				83
+#define EIC7700_CLK_DIV_G2D_DYNM			84
+#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM			85
+#define EIC7700_CLK_DIV_CRYPTO_DYNM			86
+#define EIC7700_CLK_DIV_VI_DW_DYNM			87
+#define EIC7700_CLK_DIV_NPU_E31_DYNM			88
+#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM		89
+#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM			90
+#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM			91
+#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM			92
+#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM			93
+#define EIC7700_CLK_DIV_DDR_ACLK_DYNM			94
+#define EIC7700_CLK_DIV_AON_RTC_DYNM			95
+#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM		96
+#define EIC7700_CLK_DIV_VO_CEC_DYNM			97
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0		98
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1		99
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2		100
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3		101
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0		102
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1		103
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2		104
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3		105
+#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK		106
+#define EIC7700_CLK_GATE_SPLL0_FOUT2			107
+#define EIC7700_CLK_GATE_NOC_NSP_CLK			108
+#define EIC7700_CLK_GATE_BOOTSPI			109
+#define EIC7700_CLK_GATE_BOOTSPI_CFG			110
+#define EIC7700_CLK_GATE_SCPU_CORE			111
+#define EIC7700_CLK_GATE_SCPU_BUS			112
+#define EIC7700_CLK_GATE_LPCPU_CORE			113
+#define EIC7700_CLK_GATE_LPCPU_BUS			114
+#define EIC7700_CLK_GATE_GPU_ACLK			115
+#define EIC7700_CLK_GATE_GPU_GRAY_CLK			116
+#define EIC7700_CLK_GATE_GPU_CFG_CLK			117
+#define EIC7700_CLK_GATE_DSPT_ACLK			118
+#define EIC7700_CLK_GATE_DSPT_CFG_CLK			119
+#define EIC7700_CLK_GATE_D2D_ACLK			120
+#define EIC7700_CLK_GATE_D2D_CFG_CLK			121
+#define EIC7700_CLK_GATE_TCU_ACLK			122
+#define EIC7700_CLK_GATE_TCU_CFG_CLK			123
+#define EIC7700_CLK_GATE_DDRT_CFG_CLK			124
+#define EIC7700_CLK_GATE_DDRT0_P0_ACLK			125
+#define EIC7700_CLK_GATE_DDRT0_P1_ACLK			126
+#define EIC7700_CLK_GATE_DDRT0_P2_ACLK			127
+#define EIC7700_CLK_GATE_DDRT0_P3_ACLK			128
+#define EIC7700_CLK_GATE_DDRT0_P4_ACLK			129
+#define EIC7700_CLK_GATE_DDRT1_P0_ACLK			130
+#define EIC7700_CLK_GATE_DDRT1_P1_ACLK			131
+#define EIC7700_CLK_GATE_DDRT1_P2_ACLK			132
+#define EIC7700_CLK_GATE_DDRT1_P3_ACLK			133
+#define EIC7700_CLK_GATE_DDRT1_P4_ACLK			134
+#define EIC7700_CLK_GATE_TIMER_CLK_0			135
+#define EIC7700_CLK_GATE_TIMER_CLK_1			136
+#define EIC7700_CLK_GATE_TIMER_CLK_2			137
+#define EIC7700_CLK_GATE_TIMER_CLK_3			138
+#define EIC7700_CLK_GATE_TIMER_PCLK_0			139
+#define EIC7700_CLK_GATE_TIMER_PCLK_1			140
+#define EIC7700_CLK_GATE_TIMER_PCLK_2			141
+#define EIC7700_CLK_GATE_TIMER_PCLK_3			142
+#define EIC7700_CLK_GATE_TIMER3_CLK8			143
+#define EIC7700_CLK_GATE_PCIET_ACLK			144
+#define EIC7700_CLK_GATE_PCIET_CFG_CLK			145
+#define EIC7700_CLK_GATE_PCIET_CR_CLK			146
+#define EIC7700_CLK_GATE_PCIET_AUX_CLK			147
+#define EIC7700_CLK_GATE_NPU_ACLK			148
+#define EIC7700_CLK_GATE_NPU_CFG_CLK			149
+#define EIC7700_CLK_GATE_NPU_LLC_ACLK			150
+#define EIC7700_CLK_GATE_NPU_CLK			151
+#define EIC7700_CLK_GATE_NPU_E31_CLK			152
+#define EIC7700_CLK_GATE_VI_ACLK			153
+#define EIC7700_CLK_GATE_VI_DVP_CLK			154
+#define EIC7700_CLK_GATE_VI_CFG_CLK			155
+#define EIC7700_CLK_GATE_VI_DIG_DW_CLK			156
+#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK			157
+#define EIC7700_CLK_GATE_VI_SHUTTER_0			158
+#define EIC7700_CLK_GATE_VI_SHUTTER_1			159
+#define EIC7700_CLK_GATE_VI_SHUTTER_2			160
+#define EIC7700_CLK_GATE_VI_SHUTTER_3			161
+#define EIC7700_CLK_GATE_VI_SHUTTER_4			162
+#define EIC7700_CLK_GATE_VI_SHUTTER_5			163
+#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC		164
+#define EIC7700_CLK_GATE_VI_PHY_CFG			165
+#define EIC7700_CLK_GATE_VO_ACLK			166
+#define EIC7700_CLK_GATE_VO_CFG_CLK			167
+#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK		168
+#define EIC7700_CLK_GATE_VO_PIXEL_CLK			169
+#define EIC7700_CLK_GATE_VO_I2S_MCLK			170
+#define EIC7700_CLK_GATE_HSP_CFG_CLK			171
+#define EIC7700_CLK_GATE_VC_ACLK			172
+#define EIC7700_CLK_GATE_VC_CFG_CLK			173
+#define EIC7700_CLK_GATE_VC_JE_CLK			174
+#define EIC7700_CLK_GATE_VC_JD_CLK			175
+#define EIC7700_CLK_GATE_VC_VE_CLK			176
+#define EIC7700_CLK_GATE_VC_VD_CLK			177
+#define EIC7700_CLK_GATE_G2D_CFG_CLK			178
+#define EIC7700_CLK_GATE_G2D_CLK			179
+#define EIC7700_CLK_GATE_G2D_ACLK			180
+#define EIC7700_CLK_GATE_AONDMA_CFG			181
+#define EIC7700_CLK_GATE_AONDMA_ACLK			182
+#define EIC7700_CLK_GATE_AON_ACLK			183
+#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK		184
+#define EIC7700_CLK_GATE_VO_CR_CLK			185
+#define EIC7700_CLK_GATE_HSP_ACLK			186
+#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK		187
+#define EIC7700_CLK_GATE_RTC_CFG			188
+#define EIC7700_CLK_GATE_RTC				189
+#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK		190
+#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK		191
+#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK		192
+#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK		193
+#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK		194
+#define EIC7700_CLK_GATE_HSP_RMII_REF_0			195
+#define EIC7700_CLK_GATE_HSP_RMII_REF_1			196
+#define EIC7700_CLK_GATE_PKA_CFG			197
+#define EIC7700_CLK_GATE_SPACC_CFG			198
+#define EIC7700_CLK_GATE_CRYPTO				199
+#define EIC7700_CLK_GATE_TRNG_CFG			200
+#define EIC7700_CLK_GATE_OTP_CFG			201
+#define EIC7700_CLK_GATE_MAILBOX_0			202
+#define EIC7700_CLK_GATE_MAILBOX_1			203
+#define EIC7700_CLK_GATE_MAILBOX_2			204
+#define EIC7700_CLK_GATE_MAILBOX_3			205
+#define EIC7700_CLK_GATE_MAILBOX_4			206
+#define EIC7700_CLK_GATE_MAILBOX_5			207
+#define EIC7700_CLK_GATE_MAILBOX_6			208
+#define EIC7700_CLK_GATE_MAILBOX_7			209
+#define EIC7700_CLK_GATE_MAILBOX_8			210
+#define EIC7700_CLK_GATE_MAILBOX_9			211
+#define EIC7700_CLK_GATE_MAILBOX_10			212
+#define EIC7700_CLK_GATE_MAILBOX_11			213
+#define EIC7700_CLK_GATE_MAILBOX_12			214
+#define EIC7700_CLK_GATE_MAILBOX_13			215
+#define EIC7700_CLK_GATE_MAILBOX_14			216
+#define EIC7700_CLK_GATE_MAILBOX_15			217
+#define EIC7700_CLK_GATE_LSP_I2C0_PCLK			218
+#define EIC7700_CLK_GATE_LSP_I2C1_PCLK			219
+#define EIC7700_CLK_GATE_LSP_I2C2_PCLK			220
+#define EIC7700_CLK_GATE_LSP_I2C3_PCLK			221
+#define EIC7700_CLK_GATE_LSP_I2C4_PCLK			222
+#define EIC7700_CLK_GATE_LSP_I2C5_PCLK			223
+#define EIC7700_CLK_GATE_LSP_I2C6_PCLK			224
+#define EIC7700_CLK_GATE_LSP_I2C7_PCLK			225
+#define EIC7700_CLK_GATE_LSP_I2C8_PCLK			226
+#define EIC7700_CLK_GATE_LSP_I2C9_PCLK			227
+#define EIC7700_CLK_GATE_LSP_WDT0_PCLK			228
+#define EIC7700_CLK_GATE_LSP_WDT1_PCLK			229
+#define EIC7700_CLK_GATE_LSP_WDT2_PCLK			230
+#define EIC7700_CLK_GATE_LSP_WDT3_PCLK			231
+#define EIC7700_CLK_GATE_LSP_SSI0_PCLK			232
+#define EIC7700_CLK_GATE_LSP_SSI1_PCLK			233
+#define EIC7700_CLK_GATE_LSP_PVT_PCLK			234
+#define EIC7700_CLK_GATE_AON_I2C0_PCLK			235
+#define EIC7700_CLK_GATE_AON_I2C1_PCLK			236
+#define EIC7700_CLK_GATE_LSP_UART0_PCLK			237
+#define EIC7700_CLK_GATE_LSP_UART1_PCLK			238
+#define EIC7700_CLK_GATE_LSP_UART2_PCLK			239
+#define EIC7700_CLK_GATE_LSP_UART3_PCLK			240
+#define EIC7700_CLK_GATE_LSP_UART4_PCLK			241
+#define EIC7700_CLK_GATE_LSP_TIMER_PCLK			242
+#define EIC7700_CLK_GATE_LSP_FAN_PCLK			243
+#define EIC7700_CLK_GATE_LSP_PVT0_CLK			244
+#define EIC7700_CLK_GATE_LSP_PVT1_CLK			245
+#define EIC7700_CLK_GATE_VC_JE_PCLK			246
+#define EIC7700_CLK_GATE_VC_JD_PCLK			247
+#define EIC7700_CLK_GATE_VC_VE_PCLK			248
+#define EIC7700_CLK_GATE_VC_VD_PCLK			249
+#define EIC7700_CLK_GATE_VC_MON_PCLK			250
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK			251
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST		252
+#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2		253
+#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24		254
+#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10	255
+#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2	256
+#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2		257
+#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2		258
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2		259
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4		260
+#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20		261
+#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6	262
+#define EIC7700_CLK_DIV_NOC_WDREF_DYNM			263
+#define EIC7700_CLK_GATE_DDR0_TRACE			264
+#define EIC7700_CLK_GATE_DDR1_TRACE			265
+#define EIC7700_CLK_GATE_RNOC_NSP			266
+#define EIC7700_CLK_GATE_NOC_WDREF			267
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */
-- 
2.43.0