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[80.230.79.166]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a31f0330sm175946375e9.9.2026.02.22.06.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Feb 2026 06:38:38 -0800 (PST) Date: Sun, 22 Feb 2026 09:38:36 -0500 From: "Michael S. Tsirkin" To: Saif Abrar Cc: qemu-devel@nongnu.org Subject: Re: [PATCH v3 0/9] : pnv/phb4: Update PHB4 to the latest PHB5 spec Message-ID: <20260222092651-mutt-send-email-mst@kernel.org> References: <20251230102156.886288-1-saif.abrar@linux.vnet.ibm.com> <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com> <20260220112141-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.798, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.79, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, Feb 21, 2026 at 12:35:15PM +0530, Saif Abrar wrote: > Hello Michael, > > Thanks for informing! > > Trying to understand why it's breaking now? (as it must be building earlier) > > Any insights will be helpful. > > Regards, > > Saif I think clang rejects declarations placed directly after case labels in a switch. clang sees this pattern: case PHB_PCIE_DLP_TRAIN_CTL: PCIHostState *pci = ... as invalid, so it throws "expected expression" > > On 20-02-2026 09:52 pm, Michael S. Tsirkin wrote: > > On Tue, Feb 10, 2026 at 07:40:50AM -0600, Saif Abrar wrote: > > > Hello, > > > > > > Addressing the review comments for the series v2: > > > https://lists.gnu.org/archive/html/qemu-devel/2025-12/msg03768.html > > > > breaks tsan build: > > > > > > https://gitlab.com/mstredhat/qemu/-/jobs/13201554945 > > > > ../hw/pci-host/pnv_phb4.c:968:9: error: expected expression > > PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > > ^ > > ../hw/pci-host/pnv_phb4.c:969:43: error: use of undeclared identifier 'pci' > > PCIDevice *pdev = pci_find_device(pci->bus, 0, 0); > > ^ > > ../hw/pci-host/pnv_phb4.c:999:9: error: use of undeclared identifier 'pci' > > pci = PCI_HOST_BRIDGE(phb->phb_base); > > ^ > > ../hw/pci-host/pnv_phb4.c:1000:32: error: use of undeclared identifier 'pci' > > pdev = pci_find_device(pci->bus, 0, 0); > > ^ > > 4 errors generated. > > > > > > > This series updates the existing PHB4 model to the latest spec: > > > "Power Systems Host Bridge 5 (PHB5) Functional Specification Version 0.5_00". > > > > > > Updates include the following: > > > - implemented sticky reset logic > > > - implemented read-only, write-only, W1C and WxC logic > > > - return all 1's on read to unimplemented registers > > > - update PCIE registers for link status, speed and width > > > - implement IODA PCT debug table without any functionality > > > - update LSI Source-ID register based on small/big PHB number of interrupts > > > > > > Also, a new testbench for PHB4 model is added that does XSCOM read/writes > > > to various registers of interest and verifies the values. > > > > > > Regards. > > > > > > Saif Abrar (9): > > > qtest/phb4: Add testbench for PHB4 > > > pnv/phb4: Add reset logic to PHB4 > > > pnv/phb4: Implement sticky reset logic in PHB4 > > > pnv/phb4: Implement read-only and write-only bits of registers > > > pnv/phb4: Implement write-clear and return 1's on unimplemented reg read > > > pnv/phb4: Set link-active status in HPSTAT and LMR registers > > > pnv/phb4: Set link speed and width in the DLP training control register > > > pnv/phb4: Implement IODA PCT table > > > pnv/phb4: Mask off LSI Source-ID based on number of interrupts > > > > > > hw/pci-host/pnv_phb.c | 1 + > > > hw/pci-host/pnv_phb4.c | 583 +++++++++++++++++++++++++--- > > > include/hw/pci-host/pnv_phb4.h | 16 +- > > > include/hw/pci-host/pnv_phb4_regs.h | 66 +++- > > > tests/qtest/meson.build | 1 + > > > tests/qtest/pnv-phb4-test.c | 228 +++++++++++ > > > 6 files changed, 837 insertions(+), 58 deletions(-) > > > create mode 100644 tests/qtest/pnv-phb4-test.c > > > > > > -- > > > 2.47.3