Re: [PATCH 05/12] drm/tyr: add MMU address space registers

[Boris Brezillon <boris.brezillon@collabora.com>]

On Sat, 21 Feb 2026 09:09:23 +0000
Alice Ryhl <aliceryhl@google.com> wrote:

> On Wed, Feb 11, 2026 at 05:37:06PM -0800, Deborah Brouwer wrote:
> > From: Boris Brezillon <boris.brezillon@collabora.com>
> > 
> > Add register definitions and constants for managing MMU address space,
> > including:
> >   - Address space translation configuration (page table format, attributes)
> >   - Memory attributes (cacheability, shareability)
> >   - Address space commands (update, lock, flush)
> >   - AsRegister helper for per-AS register access
> > 
> > These will be used by the MMU/VM manager to configure page tables and
> > control address space operations.
> > 
> > Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
> > Co-developed-by: Deborah Brouwer <deborah.brouwer@collabora.com>
> > Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>  
> 
> Reviewed-by: Alice Ryhl <aliceryhl@google.com>
> 
> > +/// Maximum number of hardware address space slots.
> > +/// The actual number of slots available is usually much lower.
> > +pub(crate) const MAX_AS_REGISTERS: usize = 32;  
> 
> Not necessarily a problem, but this constant is not present in Panthor's
> header file.

BTW, I think the max is 16 not 32.