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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit :::::: :::::: Manual check reason: "__compiletime_assert_NNN" :::::: BCC: lkp@intel.com CC: llvm@lists.linux.dev CC: oe-kbuild-all@lists.linux.dev In-Reply-To: <20260223-t_power_on_fux-v2-2-20c921262709@oss.qualcomm.com> References: <20260223-t_power_on_fux-v2-2-20c921262709@oss.qualcomm.com> TO: Krishna Chaitanya Chundru TO: Manivannan Sadhasivam TO: Lorenzo Pieralisi TO: "Krzysztof Wilczyński" TO: Rob Herring TO: Bjorn Helgaas TO: Jingoo Han CC: linux-pci@vger.kernel.org CC: linux-arm-msm@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: mayank.rana@oss.qualcomm.com CC: quic_vbadigan@quicinc.com CC: Krishna Chaitanya Chundru Hi Krishna, kernel test robot noticed the following build errors: [auto build test ERROR on 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f] url: https://github.com/intel-lab-lkp/linux/commits/Krishna-Chaitanya-Chundru/PCI-ASPM-Add-helper-to-encode-L1SS-T_POWER_ON-fields/20260223-192621 base: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f patch link: https://lore.kernel.org/r/20260223-t_power_on_fux-v2-2-20c921262709%40oss.qualcomm.com patch subject: [PATCH v2 2/3] PCI: dwc: Add helper to Program T_POWER_ON :::::: branch date: 13 hours ago :::::: commit date: 13 hours ago config: x86_64-randconfig-014-20260224 (https://download.01.org/0day-ci/archive/20260224/202602240816.o0QnIVMF-lkp@intel.com/config) compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260224/202602240816.o0QnIVMF-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/r/202602240816.o0QnIVMF-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/pci/controller/dwc/pcie-designware.c:1270:10: error: call to '__compiletime_assert_539' declared with 'error' attribute: FIELD_PREP: value too large for the field 1270 | val |= FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_SCALE, scale); | ^ include/linux/bitfield.h:138:3: note: expanded from macro 'FIELD_PREP' 138 | __FIELD_PREP(_mask, _val, "FIELD_PREP: "); \ | ^ include/linux/bitfield.h:91:3: note: expanded from macro '__FIELD_PREP' 91 | __BF_FIELD_CHECK_MASK(mask, val, pfx); \ | ^ include/linux/bitfield.h:70:3: note: expanded from macro '__BF_FIELD_CHECK_MASK' 70 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \ | ^ note: (skipping 2 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) include/linux/compiler_types.h:694:2: note: expanded from macro '_compiletime_assert' 694 | __compiletime_assert(condition, msg, prefix, suffix) | ^ include/linux/compiler_types.h:687:4: note: expanded from macro '__compiletime_assert' 687 | prefix ## suffix(); \ | ^ :28:1: note: expanded from here 28 | __compiletime_assert_539 | ^ 1 error generated. vim +1270 drivers/pci/controller/dwc/pcie-designware.c a00bba406b5a68 Bjorn Helgaas 2025-11-18 1251 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1252 /* TODO: Need to handle multi root ports */ 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1253 void dw_pcie_program_t_power_on(struct dw_pcie *pci, u16 t_power_on) 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1254 { 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1255 u8 scale, value; 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1256 u16 offset; 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1257 u32 val; 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1258 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1259 if (!t_power_on) 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1260 return; 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1261 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1262 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1263 if (offset) { 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1264 pcie_encode_t_power_on(t_power_on, &scale, &value); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1265 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1266 dw_pcie_dbi_ro_wr_en(pci); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1267 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1268 val = readl(pci->dbi_base + offset + PCI_L1SS_CAP); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1269 val &= ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 @1270 val |= FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_SCALE, scale); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1271 val |= FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_VALUE, value); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1272 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1273 writel(val, pci->dbi_base + offset + PCI_L1SS_CAP); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1274 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1275 dw_pcie_dbi_ro_wr_dis(pci); 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1276 } 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1277 } 23b85f7abefda8 Krishna Chaitanya Chundru 2026-02-23 1278 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki