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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82739ff3667sm912196b3a.41.2026.02.25.21.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 21:13:52 -0800 (PST) From: phucduc.bui@gmail.com To: dri-devel@lists.freedesktop.org Cc: laurent.pinchart@ideasonboard.com, geert+renesas@glider.be, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, phucduc.bui@gmail.com Subject: [PATCH] drm: shmobile: Fix blank screen after resume when LCDC is stopped Date: Thu, 26 Feb 2026 12:13:38 +0700 Message-ID: <20260226051338.27460-1-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc The LCDC controller on R8A7740 loses its register state during deep sleep. Upon resume, the driver's Mirror Register mechanism (MRS) fails to update active registers because the controller is stopped (DO=0). According to the datasheet (Section 38.7.1, Figure 38.13), the Two-Set Register Switching logic only triggers a change between Set A and Set B when a Frame End Interrupt occurs at the completion of a display frame. During resume, as the LCDC is stopped, no frame is processed and no Frame End pulse is generated. This leaves the Display Data Start Address (SA) pending in the standby set, while the active register (Side A) remains at 0x00000000, preventing the display engine from starting.Debug logs collected during resume confirm this behavior, showing the start address written to the standby set while the active register remains unchanged. Prime both register sets when the LCDC is stopped: If DO=0: Use lcdc_write() to force the Start Address (SA) into both Set A and Set B registers. This bypasses the switching logic and ensures the engine has a valid base address immediately upon being enabled. If DO=1: Maintain the standard Mirror mechanism and MRS toggle for normal, tear-free operation. Verified on R8A7740. Signed-off-by: bui duc phuc --- .../gpu/drm/renesas/shmobile/shmob_drm_plane.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c index 9d166ab2af8b..21fd1e19beda 100644 --- a/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c +++ b/drivers/gpu/drm/renesas/shmobile/shmob_drm_plane.c @@ -70,6 +70,7 @@ static void shmob_drm_primary_plane_setup(struct shmob_drm_plane *splane, struct shmob_drm_plane_state *sstate = to_shmob_plane_state(state); struct shmob_drm_device *sdev = to_shmob_device(splane->base.dev); struct drm_framebuffer *fb = state->fb; + u32 ldcnt2r; /* TODO: Handle YUV colorspaces. Hardcode REC709 for now. */ lcdc_write(sdev, LDDFR, sstate->format->lddfr | LDDFR_CF1); @@ -78,11 +79,19 @@ static void shmob_drm_primary_plane_setup(struct shmob_drm_plane *splane, /* Word and long word swap. */ lcdc_write(sdev, LDDDSR, sstate->format->ldddsr); - lcdc_write_mirror(sdev, LDSA1R, sstate->dma[0]); - if (shmob_drm_format_is_yuv(sstate->format)) - lcdc_write_mirror(sdev, LDSA2R, sstate->dma[1]); + ldcnt2r = lcdc_read(sdev, LDCNT2R); + + if (ldcnt2r & LDCNT2R_DO) { + lcdc_write_mirror(sdev, LDSA1R, sstate->dma[0]); + if (shmob_drm_format_is_yuv(sstate->format)) + lcdc_write_mirror(sdev, LDSA2R, sstate->dma[1]); - lcdc_write(sdev, LDRCNTR, lcdc_read(sdev, LDRCNTR) ^ LDRCNTR_MRS); + lcdc_write(sdev, LDRCNTR, lcdc_read(sdev, LDRCNTR) ^ LDRCNTR_MRS); + } else { + lcdc_write(sdev, LDSA1R, sstate->dma[0]); + if (shmob_drm_format_is_yuv(sstate->format)) + lcdc_write_mirror(sdev, LDSA2R, sstate->dma[1]); + } } static void shmob_drm_overlay_plane_setup(struct shmob_drm_plane *splane, -- 2.43.0