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Fri, 27 Feb 2026 10:11:43 -0800 (PST) From: Lucas Faria Mendes To: gregkh@linuxfoundation.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ovidiu.panait.oss@gmail.com Cc: devicetree@vger.kernel.org, linux-staging@lists.linux.dev, Lucas Faria Mendes Subject: [PATCH v2 2/3] dt-bindings: misc: xlnx,axi-fifo-mm-s: convert to json-schema Date: Fri, 27 Feb 2026 15:10:44 -0300 Message-ID: <20260227181051.36207-3-lucas.fariamo08@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260227181051.36207-1-lucas.fariamo08@gmail.com> References: <20260227-unboxed-customary-7ce6eda1858c@spud> <20260227181051.36207-1-lucas.fariamo08@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit --- .../bindings/misc/xlnx,axi-fifo-mm-s.yaml | 91 ++++++++++++++++++ drivers/staging/axis-fifo/axis-fifo.txt | 96 ------------------- 2 files changed, 91 insertions(+), 96 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml delete mode 100644 drivers/staging/axis-fifo/axis-fifo.txt diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml new file mode 100644 index 000000000000..967d681f3980 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI-Stream FIFO IP core + +maintainers: + - Jacob Feder + +description: | + The Xilinx AXI-Stream FIFO IP core has read and write AXI-Stream FIFOs, + the contents of which can be accessed from the AXI4 memory-mapped interface. + This is useful for transferring data from a processor into the FPGA fabric. + + See Xilinx PG080 document for IP details. + + Currently supports only store-forward mode with a 32-bit AXI4-Lite + interface. + +properties: + compatible: + enum: + - xlnx,axi-fifo-mm-s-4.1 + - xlnx,axi-fifo-mm-s-4.2 + - xlnx,axi-fifo-mm-s-4.3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: interrupt + + xlnx,axi-str-rxd-tdata-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + AXI-Stream RX data width in bits. Only 32-bit is supported. + + xlnx,axi-str-txd-tdata-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + AXI-Stream TX data width in bits. Only 32-bit is supported. + + xlnx,rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Depth of RX FIFO in words. + + xlnx,tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Depth of TX FIFO in words. + + xlnx,use-rx-data: + type: boolean + description: RX FIFO is enabled. + + xlnx,use-tx-data: + type: boolean + description: TX FIFO is enabled. + +required: + - compatible + - reg + - interrupts + - xlnx,axi-str-rxd-tdata-width + - xlnx,axi-str-txd-tdata-width + - xlnx,rx-fifo-depth + - xlnx,tx-fifo-depth + +additionalProperties: false + +examples: + - | + dma-controller@43c00000 { + compatible = "xlnx,axi-fifo-mm-s-4.1"; + reg = <0x43c00000 0x10000>; + interrupt-names = "interrupt"; + interrupt-parent = <&intc>; + interrupts = <0 29 4>; + xlnx,axi-str-rxd-tdata-width = <32>; + xlnx,axi-str-txd-tdata-width = <32>; + xlnx,rx-fifo-depth = <512>; + xlnx,tx-fifo-depth = <32768>; + xlnx,use-tx-data; + }; diff --git a/drivers/staging/axis-fifo/axis-fifo.txt b/drivers/staging/axis-fifo/axis-fifo.txt deleted file mode 100644 index 413b81a53202..000000000000 --- a/drivers/staging/axis-fifo/axis-fifo.txt +++ /dev/null @@ -1,96 +0,0 @@ -Xilinx AXI-Stream FIFO v4.1 IP core - -This IP core has read and write AXI-Stream FIFOs, the contents of which can -be accessed from the AXI4 memory-mapped interface. This is useful for -transferring data from a processor into the FPGA fabric. The driver creates -a character device that can be read/written to with standard -open/read/write/close. - -See Xilinx PG080 document for IP details. - -Currently supports only store-forward mode with a 32-bit -AXI4-Lite interface. DOES NOT support: - - cut-through mode - - AXI4 (non-lite) - -Required properties: -- compatible: Should be one of: - "xlnx,axi-fifo-mm-s-4.1" - "xlnx,axi-fifo-mm-s-4.2" - "xlnx,axi-fifo-mm-s-4.3" -- interrupt-names: Should be "interrupt" -- interrupt-parent: Should be <&intc> -- interrupts: Should contain interrupts lines. -- reg: Should contain registers location and length. -- xlnx,axi-str-rxd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA" -- xlnx,axi-str-rxd-tdata-width: Should be <0x20> -- xlnx,axi-str-txc-protocol: Should be "XIL_AXI_STREAM_ETH_CTRL" -- xlnx,axi-str-txc-tdata-width: Should be <0x20> -- xlnx,axi-str-txd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA" -- xlnx,axi-str-txd-tdata-width: Should be <0x20> -- xlnx,axis-tdest-width: AXI-Stream TDEST width (ignored by the driver) -- xlnx,axis-tid-width: AXI-Stream TID width (ignored by the driver) -- xlnx,axis-tuser-width: AXI-Stream TUSER width (ignored by the driver) -- xlnx,data-interface-type: Should be <0x0> (ignored by the driver) -- xlnx,has-axis-tdest: Should be <0x0> (this feature isn't supported) -- xlnx,has-axis-tid: Should be <0x0> (this feature isn't supported) -- xlnx,has-axis-tkeep: Should be <0x0> (this feature isn't supported) -- xlnx,has-axis-tstrb: Should be <0x0> (this feature isn't supported) -- xlnx,has-axis-tuser: Should be <0x0> (this feature isn't supported) -- xlnx,rx-fifo-depth: Depth of RX FIFO in words -- xlnx,rx-fifo-pe-threshold: RX programmable empty interrupt threshold - (ignored by the driver) -- xlnx,rx-fifo-pf-threshold: RX programmable full interrupt threshold - (ignored by the driver) -- xlnx,s-axi-id-width: Should be <0x4> (ignored by the driver) -- xlnx,s-axi4-data-width: Should be <0x20> (ignored by the driver) -- xlnx,select-xpm: Should be <0x0> (ignored by the driver) -- xlnx,tx-fifo-depth: Depth of TX FIFO in words -- xlnx,tx-fifo-pe-threshold: TX programmable empty interrupt threshold - (ignored by the driver) -- xlnx,tx-fifo-pf-threshold: TX programmable full interrupt threshold - (ignored by the driver) -- xlnx,use-rx-cut-through: Should be <0x0> (this feature isn't supported) -- xlnx,use-rx-data: <0x1> if RX FIFO is enabled, <0x0> otherwise -- xlnx,use-tx-ctrl: Should be <0x0> (this feature isn't supported) -- xlnx,use-tx-cut-through: Should be <0x0> (this feature isn't supported) -- xlnx,use-tx-data: <0x1> if TX FIFO is enabled, <0x0> otherwise - -Example: - -axi_fifo_mm_s_0: axi_fifo_mm_s@43c00000 { - compatible = "xlnx,axi-fifo-mm-s-4.1"; - interrupt-names = "interrupt"; - interrupt-parent = <&intc>; - interrupts = <0 29 4>; - reg = <0x43c00000 0x10000>; - xlnx,axi-str-rxd-protocol = "XIL_AXI_STREAM_ETH_DATA"; - xlnx,axi-str-rxd-tdata-width = <0x20>; - xlnx,axi-str-txc-protocol = "XIL_AXI_STREAM_ETH_CTRL"; - xlnx,axi-str-txc-tdata-width = <0x20>; - xlnx,axi-str-txd-protocol = "XIL_AXI_STREAM_ETH_DATA"; - xlnx,axi-str-txd-tdata-width = <0x20>; - xlnx,axis-tdest-width = <0x4>; - xlnx,axis-tid-width = <0x4>; - xlnx,axis-tuser-width = <0x4>; - xlnx,data-interface-type = <0x0>; - xlnx,has-axis-tdest = <0x0>; - xlnx,has-axis-tid = <0x0>; - xlnx,has-axis-tkeep = <0x0>; - xlnx,has-axis-tstrb = <0x0>; - xlnx,has-axis-tuser = <0x0>; - xlnx,rx-fifo-depth = <0x200>; - xlnx,rx-fifo-pe-threshold = <0x2>; - xlnx,rx-fifo-pf-threshold = <0x1fb>; - xlnx,s-axi-id-width = <0x4>; - xlnx,s-axi4-data-width = <0x20>; - xlnx,select-xpm = <0x0>; - xlnx,tx-fifo-depth = <0x8000>; - xlnx,tx-fifo-pe-threshold = <0x200>; - xlnx,tx-fifo-pf-threshold = <0x7ffb>; - xlnx,use-rx-cut-through = <0x0>; - xlnx,use-rx-data = <0x0>; - xlnx,use-tx-ctrl = <0x0>; - xlnx,use-tx-cut-through = <0x0>; - xlnx,use-tx-data = <0x1>; -}; -- 2.53.0