From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1287104893B for ; Sat, 28 Feb 2026 01:35:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4540310EC6A; Sat, 28 Feb 2026 01:35:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dmIo9gN2"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 85A3D10EC53 for ; Sat, 28 Feb 2026 01:35:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772242513; x=1803778513; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aOjqdMlwY7ZfY/faE+kSciseocq3UHNNRbQycTGcpus=; b=dmIo9gN2bYD1e0Wqc0khxmP8PvRR4w7UZnlMBaa3npyZl4J0BuGOxDrd 8N8u4inn5afOcWEJjj7EBWQSLxC4kUduNLbWqORHLhlmqSriPhbxBg1xC 8CLLnTvdssHJKqiYI7OnktUCMYpn2c8CCyL0SL6D3ttO/u7g35YusYZHw 6MbeFV+lXI4SHbf6flwcho19yyOfvTg1Jfb1j7K7do2WKO4WQc9NePJc/ lCEt2sWYmXw5g5nv7Nn73db2gR6tXIQKn8HOCvAMrleN9HKB9q/Iy+uzz OqiAGle+Gaf8u8pcPEeHLquu7jKYqMAfzQhFDvxgnuxgP3XYT9m598ScO A==; X-CSE-ConnectionGUID: 8Hr3wtR3T2WOzU6c+M0XdQ== X-CSE-MsgGUID: RDJRh6JkTOSnLwMXbUnjaQ== X-IronPort-AV: E=McAfee;i="6800,10657,11714"; a="83966358" X-IronPort-AV: E=Sophos;i="6.21,315,1763452800"; d="scan'208";a="83966358" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2026 17:35:08 -0800 X-CSE-ConnectionGUID: 3Tyu9lQMQ7SZcOZsCGD1iA== X-CSE-MsgGUID: JRrsKLRjQFezh217yEZghw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,315,1763452800"; d="scan'208";a="213854893" Received: from lstrano-desk.jf.intel.com ([10.54.39.91]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2026 17:35:09 -0800 From: Matthew Brost To: intel-xe@lists.freedesktop.org Cc: stuart.summers@intel.com, arvind.yadav@intel.com, himal.prasad.ghimiray@intel.com, thomas.hellstrom@linux.intel.com, francois.dugast@intel.com Subject: [PATCH v3 19/25] drm/xe: Add ULLS support to LRC Date: Fri, 27 Feb 2026 17:34:55 -0800 Message-Id: <20260228013501.106680-20-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260228013501.106680-1-matthew.brost@intel.com> References: <20260228013501.106680-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Define memory layout for ULLS semaphores stored in LRC memory. Add support functions to return GGTT address and set semaphore based on a job's seqno. Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_lrc.c | 51 +++++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_lrc.h | 3 ++ drivers/gpu/drm/xe/xe_lrc_types.h | 4 +++ 3 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c index 384f9b31421e..44fb600bd228 100644 --- a/drivers/gpu/drm/xe/xe_lrc.c +++ b/drivers/gpu/drm/xe/xe_lrc.c @@ -718,6 +718,7 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc) #define LRC_CTX_JOB_TIMESTAMP_OFFSET 512 #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024 #define LRC_PARALLEL_PPHWSP_OFFSET 2048 +#define LRC_ULLS_PPHWSP_OFFSET 2048 /* Mutually exclusive with parallel */ #define LRC_SEQNO_OFFSET 0 #define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8) @@ -773,6 +774,12 @@ static inline u32 __xe_lrc_engine_id_offset(struct xe_lrc *lrc) return xe_lrc_pphwsp_offset(lrc) + LRC_ENGINE_ID_PPHWSP_OFFSET; } +static u32 __xe_lrc_ulls_offset(struct xe_lrc *lrc) +{ + /* The ulls is stored in the driver-defined portion of PPHWSP */ + return xe_lrc_pphwsp_offset(lrc) + LRC_ULLS_PPHWSP_OFFSET; +} + static u32 __xe_lrc_ctx_timestamp_offset(struct xe_lrc *lrc) { return __xe_lrc_regs_offset(lrc) + CTX_TIMESTAMP * sizeof(u32); @@ -830,6 +837,7 @@ DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo) DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo) DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo) DECL_MAP_ADDR_HELPERS(parallel, lrc->bo) +DECL_MAP_ADDR_HELPERS(ulls, lrc->bo) DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo) DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo) @@ -1860,6 +1868,49 @@ static u32 xe_lrc_engine_id(struct xe_lrc *lrc) return xe_map_read32(xe, &map); } +#define semaphore_offset(seqno) \ + (sizeof(u32) * ((seqno) % LRC_MIGRATION_ULLS_SEMAPORE_COUNT)) + +/** + * xe_lrc_ulls_semaphore_ggtt_addr() - ULLS semaphore GGTT address + * @lrc: Pointer to the lrc. + * @seqno: seqno of current job. + * + * Calculate ULLS semaphore GGTT address based on input seqno + * + * Returns: ULLS semaphore GGTT address + */ +u32 xe_lrc_ulls_semaphore_ggtt_addr(struct xe_lrc *lrc, u32 seqno) +{ + xe_assert(lrc_to_xe(lrc), semaphore_offset(seqno) < + LRC_PPHWSP_SIZE - LRC_ULLS_PPHWSP_OFFSET); + + return __xe_lrc_ulls_ggtt_addr(lrc) + semaphore_offset(seqno); +} + +/** + * xe_lrc_set_ulls_semaphore() - Set ULLS semaphore + * @lrc: Pointer to the lrc. + * @seqno: seqno of current job. + * + * Set ULLS semaphore based on input seqno + */ +void xe_lrc_set_ulls_semaphore(struct xe_lrc *lrc, u32 seqno) +{ + struct xe_device *xe = lrc_to_xe(lrc); + struct iosys_map map = __xe_lrc_ulls_map(lrc); + + xe_assert(xe, semaphore_offset(seqno) < + LRC_PPHWSP_SIZE - LRC_ULLS_PPHWSP_OFFSET); + + xe_device_wmb(xe); /* Ensure everything before in code is ordered */ + + iosys_map_incr(&map, semaphore_offset(seqno)); + xe_map_write32(xe, &map, LRC_MIGRATION_ULLS_SEMAPORE_SINGAL); + + xe_device_wmb(xe); /* Flush write to hardware */ +} + static int instr_dw(u32 cmd_header) { /* GFXPIPE "SINGLE_DW" opcodes are a single dword */ diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h index 48f7c26cf129..9e51222191ea 100644 --- a/drivers/gpu/drm/xe/xe_lrc.h +++ b/drivers/gpu/drm/xe/xe_lrc.h @@ -111,6 +111,9 @@ void xe_default_lrc_update_memirq_regs_with_address(struct xe_hw_engine *hwe); void xe_lrc_update_memirq_regs_with_address(struct xe_lrc *lrc, struct xe_hw_engine *hwe, u32 *regs); +u32 xe_lrc_ulls_semaphore_ggtt_addr(struct xe_lrc *lrc, u32 seqno); +void xe_lrc_set_ulls_semaphore(struct xe_lrc *lrc, u32 seqno); + u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr); void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val); diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h index 5a718f759ed6..7cf84e32f998 100644 --- a/drivers/gpu/drm/xe/xe_lrc_types.h +++ b/drivers/gpu/drm/xe/xe_lrc_types.h @@ -12,6 +12,10 @@ struct xe_bo; +#define LRC_MIGRATION_ULLS_SEMAPORE_COUNT 64 /* Must be pow2 */ +#define LRC_MIGRATION_ULLS_SEMAPORE_CLEAR 0 +#define LRC_MIGRATION_ULLS_SEMAPORE_SINGAL 1 + /** * struct xe_lrc - Logical ring context (LRC) and submission ring object */ -- 2.34.1