From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E222B421EFD for ; Mon, 2 Mar 2026 16:58:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772470689; cv=none; b=UthcsKZNwedVE2mtMj1eR5bIwzP9x3VI0nm8Px6xKWmCzMLzl/xsmn0SDOwr2HFQkzwjINpsTusYfplmAlwidbdr3zm0PViUYK+UqTfTOzy+ITXZ34EW+/7PXnMY4zA7MvoPAyF/1vyH+meFM8d74RaDu3rV1iehD1vceJ1lk7o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772470689; c=relaxed/simple; bh=6gYcArx1LlhOU54aVuFbs1FPwyP5qxHMs8ZYcJrLijY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hjL9FrbbPi1Ma0obi4Dy4J9ZwjaLSjI/7R9txxMgCPifojmzM/JDFct2gKVAyW8zSrwb1OBAMK/sL8gTfZ0dNvUZ82OLNFlxV3OExVWN/qwd9SaqEDYUR9DAupqkfVEzmgsB5FpuUFf6kGIfapdjDq/eLxKsQROgn5DTHy2ek6E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73D62C19423; Mon, 2 Mar 2026 16:58:07 +0000 (UTC) From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org Cc: Will Deacon , Marc Zyngier , Oliver Upton , Lorenzo Pieralisi , Sudeep Holla , James Morse , Mark Rutland , Mark Brown , kvmarm@lists.linux.dev Subject: [PATCH 1/4] arm64: tlb: Use __tlbi_sync_s1ish_kernel() for kernel TLB maintenance Date: Mon, 2 Mar 2026 16:57:54 +0000 Message-ID: <20260302165801.3014607-2-catalin.marinas@arm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260302165801.3014607-1-catalin.marinas@arm.com> References: <20260302165801.3014607-1-catalin.marinas@arm.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add __tlbi_sync_s1ish_kernel() similar to __tlbi_sync_s1ish() and use it for kernel TLB maintenance. Also use this function in flush_tlb_all() which is only used in relation to kernel mappings. Subsequent patches can differentiate between workarounds that apply to user only or both user and kernel. Signed-off-by: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland --- arch/arm64/include/asm/tlbflush.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 1416e652612b..19be0f7bfca5 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -191,6 +191,12 @@ static inline void __tlbi_sync_s1ish(void) __repeat_tlbi_sync(vale1is, 0); } +static inline void __tlbi_sync_s1ish_kernel(void) +{ + dsb(ish); + __repeat_tlbi_sync(vale1is, 0); +} + /* * Complete broadcast TLB maintenance issued by hyp code which invalidates * stage 1 translation information in any translation regime. @@ -299,7 +305,7 @@ static inline void flush_tlb_all(void) { dsb(ishst); __tlbi(vmalle1is); - __tlbi_sync_s1ish(); + __tlbi_sync_s1ish_kernel(); isb(); } @@ -568,7 +574,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end dsb(ishst); __flush_tlb_range_op(vaale1is, start, pages, stride, 0, TLBI_TTL_UNKNOWN, false, lpa2_is_enabled()); - __tlbi_sync_s1ish(); + __tlbi_sync_s1ish_kernel(); isb(); } @@ -582,7 +588,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) dsb(ishst); __tlbi(vaae1is, addr); - __tlbi_sync_s1ish(); + __tlbi_sync_s1ish_kernel(); isb(); }