From: Jeevan B <jeevan.b@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: mohammed.thasleem@intel.com,
dibin.moolakadan.subrahmanian@intel.com,
Jeevan B <jeevan.b@intel.com>
Subject: [PATCH i-g-t 3/4] tests/kms_vrr: Add new test for DC3CO validation with LOBF
Date: Wed, 4 Mar 2026 10:08:04 +0530 [thread overview]
Message-ID: <20260304043805.572087-4-jeevan.b@intel.com> (raw)
In-Reply-To: <20260304043805.572087-1-jeevan.b@intel.com>
Add lobf-dc3co subtest to validate DC3CO entry during link-off
between frames.
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
tests/kms_vrr.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/tests/kms_vrr.c b/tests/kms_vrr.c
index 569000fee..f8b830cc0 100644
--- a/tests/kms_vrr.c
+++ b/tests/kms_vrr.c
@@ -29,6 +29,7 @@
*/
#include "igt.h"
+#include "igt_pm.h"
#include "igt_psr.h"
#include "i915/intel_drrs.h"
#include "sw_sync.h"
@@ -80,6 +81,9 @@
*
* SUBTEST: negative-basic
* Description: Make sure that VRR should not be enabled on the Non-VRR panel.
+ *
+ * SUBTEST: lobf-dc3co
+ * Description: Test DC3CO entry during LOBF.
*/
#define NSECS_PER_SEC (1000000000ull)
@@ -942,6 +946,25 @@ test_lobf(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
igt_assert_f(lobf_enabled, "LOBF not enabled\n");
}
+static void test_lobf_dc3co(data_t *data, igt_crtc_t *crtc,
+ igt_output_t *output, uint32_t flags)
+{
+ unsigned long dc3co_count_before, dc3co_count_after;
+
+ dc3co_count_before = igt_read_dc_counter(data->debugfs_fd,
+ IGT_INTEL_CHECK_DC3CO);
+
+ test_lobf(data, crtc, output, flags);
+
+ dc3co_count_after = igt_read_dc_counter(data->debugfs_fd,
+ IGT_INTEL_CHECK_DC3CO);
+
+ igt_assert_f(dc3co_count_after > dc3co_count_before,
+ "DC3CO should be entered during link-off periods. "
+ "Before: %lu, After: %lu\n",
+ dc3co_count_before, dc3co_count_after);
+}
+
static void
test_cmrr(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
uint32_t flags)
@@ -1237,6 +1260,16 @@ int igt_main_args("drs:", long_opts, help_str, opt_handler, &data)
run_vrr_test(&data, test_lobf, TEST_LINK_OFF);
}
+
+ igt_describe("Test to validate DC3CO entry during link-off between active "
+ "frames in non-PSR operation non-PSR operation.");
+ igt_subtest_with_dynamic("lobf-dc3co") {
+ igt_require(intel_display_ver(intel_get_drm_devid(data.drm_fd)) >= 35);
+
+ igt_require_dc_counter(data.debugfs_fd, IGT_INTEL_CHECK_DC3CO);
+
+ run_vrr_test(&data, test_lobf_dc3co, TEST_LINK_OFF | IGT_INTEL_CHECK_DC3CO);
+ }
}
igt_fixture() {
--
2.43.0
next prev parent reply other threads:[~2026-03-04 4:37 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-04 4:38 [PATCH i-g-t 0/4] Enable and Add new tests for DC3CO Jeevan B
2026-03-04 4:38 ` [PATCH i-g-t 1/4] tests/intel/kms_pm_dc: Replace require with proper assertion Jeevan B
2026-04-07 9:29 ` Thasleem, Mohammed
2026-03-04 4:38 ` [PATCH i-g-t 2/4] tests/intel/kms_pm_dc: Enable DC3CO test for PSR2/PR modes Jeevan B
2026-04-09 6:06 ` Thasleem, Mohammed
2026-03-04 4:38 ` Jeevan B [this message]
2026-04-09 8:12 ` [PATCH i-g-t 3/4] tests/kms_vrr: Add new test for DC3CO validation with LOBF Thasleem, Mohammed
2026-03-04 4:38 ` [PATCH i-g-t 4/4] tests/intel/kms_pm_dc: Add new test for dc3co framedrop validation Jeevan B
2026-04-09 11:03 ` Thasleem, Mohammed
2026-03-04 7:30 ` ✓ Xe.CI.BAT: success for Enable and Add new tests for DC3CO (rev2) Patchwork
2026-03-04 7:30 ` ✓ i915.CI.BAT: " Patchwork
2026-03-05 5:30 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-05 9:52 ` ✗ i915.CI.Full: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2026-03-03 9:39 [PATCH i-g-t 0/4] Enable and Add new tests for DC3CO Jeevan B
2026-03-03 9:39 ` [PATCH i-g-t 3/4] tests/kms_vrr: Add new test for DC3CO validation with LOBF Jeevan B
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