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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-89a1fcb781fsm8074876d6.23.2026.03.04.09.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 09:45:31 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vxqHq-00000005ET5-2S2S; Wed, 04 Mar 2026 13:45:30 -0400 Date: Wed, 4 Mar 2026 13:45:30 -0400 From: Jason Gunthorpe To: Leon Romanovsky Cc: Danilo Krummrich , Peter Colberg , Bjorn Helgaas , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Miguel Ojeda , Alex Gaynor , Gary Guo , =?utf-8?B?QmrDtnJu?= Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Abdiel Janulgue , Daniel Almeida , Robin Murphy , Greg Kroah-Hartman , Dave Ertman , Ira Weiny , David Airlie , Simona Vetter , Jonathan Corbet , Xu Yilun , Tom Rix , Moritz Fischer , "Rafael J. Wysocki" , Boqun Feng , linux-pci@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Courbot , Alistair Popple , Joel Fernandes , John Hubbard , Zhi Wang , nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-fpga@vger.kernel.org, driver-core@lists.linux.dev Subject: Re: [PATCH v3 00/10] rust: pci: add abstractions for SR-IOV capability Message-ID: <20260304174530.GH964116@ziepe.ca> References: <20260303-rust-pci-sriov-v3-0-4443c35f0c88@redhat.com> <20260304084750.GW12611@unreal> <20260304141852.GF964116@ziepe.ca> <20260304142600.GB12611@unreal> <20260304162711.GI12611@unreal> <20260304164551.GG964116@ziepe.ca> <20260304170249.GJ12611@unreal> Precedence: bulk X-Mailing-List: driver-core@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260304170249.GJ12611@unreal> On Wed, Mar 04, 2026 at 07:02:49PM +0200, Leon Romanovsky wrote: > > No, illegal, and it doesn't even work right. When VFIO FLRs the PF it > > will blow up the half baked SRIOV and break everything. > > The FLR can be disabled. For example, PCI_DEV_FLAGS_NO_FLR_RESET flag > will do it. Well that would break all the security properties of VFIO. > > VFIO already has its own sriov_config support, the right flow is to > > bind the PF to VFIO and then enable sriov and do your assignments. > > VFIO started to support SR-IOV in 137e5531351d ("vfio/pci: Add > sriov_configure support"), which was added 8 years after VFIO core was > added cba3345cc494 ("vfio: VFIO core"). Well, time to upgrade, I see no reason to allow Rust drivers to further propogate these mistakes. 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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-89a1fcb781fsm8074876d6.23.2026.03.04.09.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 09:45:31 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vxqHq-00000005ET5-2S2S; Wed, 04 Mar 2026 13:45:30 -0400 Date: Wed, 4 Mar 2026 13:45:30 -0400 From: Jason Gunthorpe To: Leon Romanovsky Subject: Re: [PATCH v3 00/10] rust: pci: add abstractions for SR-IOV capability Message-ID: <20260304174530.GH964116@ziepe.ca> References: <20260303-rust-pci-sriov-v3-0-4443c35f0c88@redhat.com> <20260304084750.GW12611@unreal> <20260304141852.GF964116@ziepe.ca> <20260304142600.GB12611@unreal> <20260304162711.GI12611@unreal> <20260304164551.GG964116@ziepe.ca> <20260304170249.GJ12611@unreal> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260304170249.GJ12611@unreal> Message-ID-Hash: SFDJOSOG5PBCG4V7ZXPBMRA2EKYC43TB X-Message-ID-Hash: SFDJOSOG5PBCG4V7ZXPBMRA2EKYC43TB X-MailFrom: jgg@ziepe.ca X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: Danilo Krummrich , Bjorn Helgaas , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Miguel Ojeda , Alex Gaynor , Gary Guo , =?utf-8?B?QmrDtnJu?= Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Abdiel Janulgue , Daniel Almeida , Robin Murphy , Greg Kroah-Hartman , Dave Ertman , Ira Weiny , Simona Vetter , Jonathan Corbet , Xu Yilun , Tom Rix , Moritz Fischer , "Rafael J. Wysocki" , Boqun Feng , linux-pci@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Courbot , Alistair Popple , Joel Fernandes , Zhi Wang , nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-fpga@vger.kernel.org, driver-core@lists.linux.dev X-Mailman-Version: 3.3.8 Precedence: list List-Id: Nouveau development list Archived-At: Archived-At: List-Archive: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: On Wed, Mar 04, 2026 at 07:02:49PM +0200, Leon Romanovsky wrote: > > No, illegal, and it doesn't even work right. When VFIO FLRs the PF it > > will blow up the half baked SRIOV and break everything. > > The FLR can be disabled. For example, PCI_DEV_FLAGS_NO_FLR_RESET flag > will do it. Well that would break all the security properties of VFIO. > > VFIO already has its own sriov_config support, the right flow is to > > bind the PF to VFIO and then enable sriov and do your assignments. > > VFIO started to support SR-IOV in 137e5531351d ("vfio/pci: Add > sriov_configure support"), which was added 8 years after VFIO core was > added cba3345cc494 ("vfio: VFIO core"). Well, time to upgrade, I see no reason to allow Rust drivers to further propogate these mistakes. Jason