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From: <smadhavan@nvidia.com>
To: <bhelgaas@google.com>, <dan.j.williams@intel.com>,
	<dave.jiang@intel.com>, <jonathan.cameron@huawei.com>,
	<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
	<alison.schofield@intel.com>, <dave@stgolabs.net>
Cc: <alwilliamson@nvidia.com>, <jeshuas@nvidia.com>,
	<vsethi@nvidia.com>, <skancherla@nvidia.com>, <vaslot@nvidia.com>,
	<sdonthineni@nvidia.com>, <mhonap@nvidia.com>,
	<vidyas@nvidia.com>, <jan@nvidia.com>, <mochs@nvidia.com>,
	<dschumacher@nvidia.com>, <linux-cxl@vger.kernel.org>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	"Srirangan Madhavan" <smadhavan@nvidia.com>
Subject: [PATCH v5 3/7] cxl: Add memory offlining and cache flush helpers
Date: Fri, 6 Mar 2026 09:23:18 +0000	[thread overview]
Message-ID: <20260306092322.148765-4-smadhavan@nvidia.com> (raw)
In-Reply-To: <20260306092322.148765-1-smadhavan@nvidia.com>

From: Srirangan Madhavan <smadhavan@nvidia.com>

Add infrastructure for quiescing the CXL data path before reset:

- Memory offlining: check if CXL-backed memory is online and offline
  it via offline_and_remove_memory() before reset, per CXL
  spec requirement to quiesce all CXL.mem transactions before issuing
  CXL Reset.
- CPU cache flush: invalidate cache lines before reset
  as a safety measure after memory offline.

Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
 drivers/cxl/core/pci.c | 110 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index f96ce884a213..9e6f0c4b3cb6 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -4,6 +4,8 @@
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/device.h>
 #include <linux/delay.h>
+#include <linux/memory_hotplug.h>
+#include <linux/memregion.h>
 #include <linux/pci.h>
 #include <linux/pci-doe.h>
 #include <linux/aer.h>
@@ -869,3 +871,111 @@ int cxl_port_get_possible_dports(struct cxl_port *port)

 	return ctx.count;
 }
+
+/*
+ * CXL Reset support - core-provided reset logic for CXL devices.
+ *
+ * These functions implement the CXL reset sequence.
+ */
+
+/*
+ * If CXL memory backed by this decoder is online as System RAM, offline
+ * and remove it per CXL spec requirements before issuing CXL Reset.
+ * Returns 0 if memory was not online or was successfully offlined.
+ */
+static int __maybe_unused cxl_offline_memory(struct device *dev, void *data)
+{
+	struct cxl_endpoint_decoder *cxled;
+	struct cxl_region *cxlr;
+	struct cxl_region_params *p;
+	int rc;
+
+	if (!is_endpoint_decoder(dev))
+		return 0;
+
+	cxled = to_cxl_endpoint_decoder(dev);
+	cxlr = cxled->cxld.region;
+	if (!cxlr)
+		return 0;
+
+	p = &cxlr->params;
+	if (!p->res)
+		return 0;
+
+	if (walk_iomem_res_desc(IORES_DESC_NONE,
+				IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY,
+				p->res->start, p->res->end, NULL, NULL) <= 0)
+		return 0;
+
+	dev_info(dev, "Offlining CXL memory [%pr] for reset\n", p->res);
+
+#ifdef CONFIG_MEMORY_HOTREMOVE
+	rc = offline_and_remove_memory(p->res->start, resource_size(p->res));
+	if (rc) {
+		dev_err(dev,
+			"Failed to offline CXL memory [%pr]: %d\n",
+			p->res, rc);
+		return rc;
+	}
+#else
+	dev_err(dev, "Memory hotremove not supported, cannot offline CXL memory\n");
+	rc = -EOPNOTSUPP;
+	return rc;
+#endif
+
+	return 0;
+}
+
+static int __maybe_unused cxl_reset_prepare_memdev(struct cxl_memdev *cxlmd)
+{
+	struct cxl_port *endpoint;
+	struct device *dev;
+
+	if (!cxlmd || !cxlmd->cxlds)
+		return -ENODEV;
+
+	dev = cxlmd->cxlds->dev;
+	endpoint = cxlmd->endpoint;
+	if (!endpoint)
+		return 0;
+
+	return device_for_each_child(&endpoint->dev, NULL,
+				      cxl_offline_memory);
+}
+
+static int __maybe_unused cxl_decoder_flush_cache(struct device *dev, void *data)
+{
+	struct cxl_endpoint_decoder *cxled;
+	struct cxl_region *cxlr;
+	struct resource *res;
+
+	if (!is_endpoint_decoder(dev))
+		return 0;
+
+	cxled = to_cxl_endpoint_decoder(dev);
+	cxlr = cxled->cxld.region;
+	if (!cxlr || !cxlr->params.res)
+		return 0;
+
+	res = cxlr->params.res;
+	cpu_cache_invalidate_memregion(res->start, resource_size(res));
+	return 0;
+}
+
+static int __maybe_unused cxl_reset_flush_cpu_caches(struct cxl_memdev *cxlmd)
+{
+	struct cxl_port *endpoint;
+
+	if (!cxlmd)
+		return 0;
+
+	endpoint = cxlmd->endpoint;
+	if (!endpoint || IS_ERR(endpoint))
+		return 0;
+
+	if (!cpu_cache_has_invalidate_memregion())
+		return 0;
+
+	device_for_each_child(&endpoint->dev, NULL, cxl_decoder_flush_cache);
+	return 0;
+}
--
2.43.0


  parent reply	other threads:[~2026-03-06  9:24 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-06  9:23 [PATCH v5 0/7] CXL: Add cxl_reset sysfs attribute for PCI devices smadhavan
2026-03-06  9:23 ` [PATCH v5 1/7] PCI: Add CXL DVSEC reset and capability register definitions smadhavan
2026-03-06  9:23 ` [PATCH v5 2/7] PCI: Export pci_dev_save_and_disable() and pci_dev_restore() smadhavan
2026-03-06  9:23 ` smadhavan [this message]
2026-03-06 23:34   ` [PATCH v5 3/7] cxl: Add memory offlining and cache flush helpers Alex Williamson
2026-03-09 23:01   ` Dave Jiang
2026-03-06  9:23 ` [PATCH v5 4/7] cxl: Add multi-function sibling coordination for CXL reset smadhavan
2026-03-06 23:34   ` Alex Williamson
2026-03-06  9:23 ` [PATCH v5 5/7] cxl: Add CXL DVSEC reset sequence and flow orchestration smadhavan
2026-03-06 23:33   ` Alex Williamson
2026-03-10  0:26   ` Dave Jiang
2026-05-13  2:45   ` Dan Williams (nvidia)
2026-05-14 19:21     ` Dan Williams (nvidia)
2026-03-06  9:23 ` [PATCH v5 6/7] cxl: Add cxl_reset sysfs interface for PCI devices smadhavan
2026-03-06 23:32   ` Alex Williamson
2026-03-12 13:01   ` Jonathan Cameron
2026-03-14 20:39   ` Krzysztof Wilczyński
2026-03-06  9:23 ` [PATCH v5 7/7] Documentation: ABI: Add CXL PCI cxl_reset sysfs attribute smadhavan
2026-03-06 23:32   ` Alex Williamson
2026-03-09 22:37 ` [PATCH v5 0/7] CXL: Add cxl_reset sysfs attribute for PCI devices Dave Jiang
2026-03-09 22:40   ` Dave Jiang

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