Re: [PATCH v7 3/3] hw/cxl: Add a performant (and correct) path for the non interleaved cases

[Jonathan Cameron via qemu development <qemu-devel@nongnu.org>]

On Fri, 6 Mar 2026 12:11:51 +0000
Alireza Sanaee <alireza.sanaee@huawei.com> wrote:

> The CXL address to device decoding logic is complex because of the need to
> correctly decode fine grained interleave. The current implementation
> prevents use with KVM where executed instructions may reside in that memory
> and gives very slow performance even in TCG.
> 
> In many real cases non interleaved memory configurations are useful and for
> those we can use a more conventional memory region alias allowing similar
> performance to other memory in the system.
> 
> Whether this fast path is applicable can be established once the full set
> of HDM decoders has been committed (in whatever order the guest decides to
> commit them). As such a check is performed on each commit/uncommit of HDM
> decoder to establish if the alias should be added or removed.
> 
> Reviewed-by: Li Zhijian <lizhijian@fujitsu.com>
> Co-developed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Changes look good to me. Thanks for the quick turn around.

Jonathan

> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>