Re: ✗ Xe.CI.BAT: failure for Extra enabling patches for NVL-P (rev3)

[Matt Roper <matthew.d.roper@intel.com>]

On Mon, Mar 09, 2026 at 07:03:02PM -0300, Gustavo Sousa wrote:
> Patchwork <patchwork@emeril.freedesktop.org> writes:
> 
> > == Series Details ==
> >
> > Series: Extra enabling patches for NVL-P (rev3)
> > URL   : https://patchwork.freedesktop.org/series/162666/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c_BAT -> xe-pw-162666v3_BAT
> > ====================================================
> >
> > Summary
> > -------
> >
> >   **FAILURE**
> >
> >   Serious unknown changes coming with xe-pw-162666v3_BAT absolutely need to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the changes
> >   introduced in xe-pw-162666v3_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> >   to document this new failure mode, which will reduce false positives in CI.
> >
> >   
> >
> > Participating hosts (14 -> 12)
> > ------------------------------
> >
> >   Missing    (2): bat-adlp-vm bat-ptl-vm 
> >
> > Possible new issues
> > -------------------
> >
> >   Here are the unknown changes that may have been introduced in xe-pw-162666v3_BAT:
> >
> > ### IGT changes ###
> >
> > #### Possible regressions ####
> >
> >   * igt@xe_module_load@load:
> >     - bat-ptl-2:          [PASS][1] -> [ABORT][2]
> >    [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-ptl-2/igt@xe_module_load@load.html
> >    [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-ptl-2/igt@xe_module_load@load.html
> >     - bat-dg2-oem2:       [PASS][3] -> [ABORT][4]
> >    [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-dg2-oem2/igt@xe_module_load@load.html
> >    [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-dg2-oem2/igt@xe_module_load@load.html
> >     - bat-atsm-2:         [PASS][5] -> [ABORT][6]
> >    [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-atsm-2/igt@xe_module_load@load.html
> >    [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-atsm-2/igt@xe_module_load@load.html
> >     - bat-wcl-1:          [PASS][7] -> [ABORT][8]
> >    [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-wcl-1/igt@xe_module_load@load.html
> >    [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-wcl-1/igt@xe_module_load@load.html
> >     - bat-ptl-1:          [PASS][9] -> [ABORT][10]
> >    [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-ptl-1/igt@xe_module_load@load.html
> >    [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-ptl-1/igt@xe_module_load@load.html
> >     - bat-wcl-2:          [PASS][11] -> [ABORT][12]
> >    [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-wcl-2/igt@xe_module_load@load.html
> >    [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-wcl-2/igt@xe_module_load@load.html
> >     - bat-bmg-2:          [PASS][13] -> [ABORT][14]
> >    [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-bmg-2/igt@xe_module_load@load.html
> >    [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-bmg-2/igt@xe_module_load@load.html
> >     - bat-bmg-3:          [PASS][15] -> [ABORT][16]
> >    [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-bmg-3/igt@xe_module_load@load.html
> >    [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-bmg-3/igt@xe_module_load@load.html
> >     - bat-bmg-1:          [PASS][17] -> [ABORT][18]
> >    [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-bmg-1/igt@xe_module_load@load.html
> >    [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-bmg-1/igt@xe_module_load@load.html
> >     - bat-adlp-7:         [PASS][19] -> [ABORT][20]
> >    [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4683-50b85be0adadc4ab0b1e557627bebd7fdf1fcc3c/bat-adlp-7/igt@xe_module_load@load.html
> >    [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v3/bat-adlp-7/igt@xe_module_load@load.html
> 
> Oops. It appears we've hit a chicken-and-egg situation here. MMIO
> functions depend on device workarounds to be already initialized; device
> workarounds initialization depend on xe_sriov_probe_early(); which, in
> turn, needs to use MMIO functions.

Ah, we do still have that early MMIO device workaround in
mmio_flush_pending_writes().  I looked for that before but missed it
while grep'ing.

A quick fix would be to drop the FUNC(xe_rtp_match_not_sriov_vf) rule
from the device workaround and add it as an extra condition in the
function itself.  Then we wouldn't need to change the current placement
of device WA initialization.  Then longer term we can look into allowing
device workarounds with additional rule capabilities at varying levels
of device/GT initialization.


Matt

> 
> --
> Gustavo Sousa

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation