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From: Shawn Lin <shawn.lin@linux.dev>
To: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
	Luke Wang <ziniu.wang_1@nxp.com>, Shawn Lin <shawn.lin@linux.dev>
Subject: [PATCH v2 1/2] mmc: core: Validate UHS/DDR/HS200 timing selection for 1-bit bus width
Date: Tue, 10 Mar 2026 09:35:52 +0800	[thread overview]
Message-ID: <20260310013553.29332-2-shawn.lin@linux.dev> (raw)
In-Reply-To: <20260310013553.29332-1-shawn.lin@linux.dev>

From: Luke Wang <ziniu.wang_1@nxp.com>

UHS/DDR/HS200 modes require at least 4-bit bus support. Host controllers
that lack relevant capability registers rely on paring properties provided
by firmware, which may incorrectly set these modes. Now that mmc_validate_host_caps()
has been introduced to validate such configuration violations, let's also
add checks for UHS/DDR/HS200 modes.

This fixes an issue where, if the HS200/HS400 property is set while only
a 1-bit bus width is used, mmc_select_hs200() returns 0 without actually
performing the mode switch. Consequently, mmc_select_timing() proceeds
without falling back to mmc_select_hs(), leaving the eMMC device operating
in legacy mode (26 MHz) instead of switching to High Speed mode (52 MHz).

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
[Shawn: reword the commit msg and rework the code]
Signed-off-by: Shawn Lin <shawn.lin@linux.dev>
---

Changes in v2:
- updating the temporary variables in the middle and update host's caps(2)
  in the final. (Ulf)

 drivers/mmc/core/host.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 88c95db..a457c88 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -624,12 +624,24 @@ static int mmc_validate_host_caps(struct mmc_host *host)
 		return -EINVAL;
 	}
 
+	/* UHS/DDR/HS200 modes require at least 4-bit bus */
+	if (!(caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) &&
+	    ((caps & (MMC_CAP_UHS | MMC_CAP_DDR)) || (caps2 & MMC_CAP2_HS200))) {
+		dev_warn(dev, "drop UHS/DDR/HS200 support since 1-bit bus only\n");
+		caps &= ~(MMC_CAP_UHS | MMC_CAP_DDR);
+		caps2 &= ~MMC_CAP2_HS200;
+	}
+
+	/* HS400 and HS400ES modes require 8-bit bus */
 	if (caps2 & (MMC_CAP2_HS400_ES | MMC_CAP2_HS400) &&
 	    !(caps & MMC_CAP_8_BIT_DATA) && !(caps2 & MMC_CAP2_NO_MMC)) {
 		dev_warn(dev, "drop HS400 support since no 8-bit bus\n");
-		host->caps2 = caps2 & ~MMC_CAP2_HS400_ES & ~MMC_CAP2_HS400;
+		caps2 &= ~(MMC_CAP2_HS400_ES | MMC_CAP2_HS400);
 	}
 
+	host->caps = caps;
+	host->caps2 = caps2;
+
 	return 0;
 }
 
-- 
2.7.4


  reply	other threads:[~2026-03-10  1:36 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-10  1:35 [PATCH v2 0/2] Validate and clean up UHS/DDR/HS200 timing checks Shawn Lin
2026-03-10  1:35 ` Shawn Lin [this message]
2026-03-10  1:35 ` [PATCH v2 2/2] mmc: core: Remove checking MMC_CAP_4_BIT_DATA from mmc_host_can_uhs() Shawn Lin
2026-03-16 15:15 ` [PATCH v2 0/2] Validate and clean up UHS/DDR/HS200 timing checks Ulf Hansson

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