From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1667112584E for ; Wed, 11 Mar 2026 15:28:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0LUB-000495-V1; Wed, 11 Mar 2026 11:28:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0LU5-000408-Ua; Wed, 11 Mar 2026 11:28:31 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0LU3-00046c-EB; Wed, 11 Mar 2026 11:28:29 -0400 Received: from mail.maildlp.com (unknown [172.18.224.150]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4fWF4r06nbzHnGcR; Wed, 11 Mar 2026 23:28:12 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id E6C1D4056A; Wed, 11 Mar 2026 23:28:19 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 11 Mar 2026 15:28:19 +0000 Date: Wed, 11 Mar 2026 15:28:18 +0000 To: Peter Maydell CC: , Subject: Re: [PATCH 28/65] hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1 Message-ID: <20260311152818.00004e4e@huawei.com> In-Reply-To: <20260223170212.441276-29-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> <20260223170212.441276-29-peter.maydell@linaro.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.15] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Mon, 23 Feb 2026 17:01:35 +0000 Peter Maydell wrote: > The IRS_CR0 register has the main enable bit for the IRS, and an IDLE > bit to tell the guest when an enable/disable transition has > completed. > > The IRS_CR1 register has cacheability, shareability and cache hint > information to use for IRS memory accesses; since QEMU doesn't care > about this we can make it simply reads-as-written. > > Signed-off-by: Peter Maydell Trivial comment inline. Reviewed-by: Jonathan Cameron > --- > hw/intc/arm_gicv5.c | 14 ++++++++++++++ > hw/intc/arm_gicv5_common.c | 2 ++ > include/hw/intc/arm_gicv5_common.h | 2 ++ > 3 files changed, 18 insertions(+) > > diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c > index d1baa015d1..5f4c4158c4 100644 > --- a/hw/intc/arm_gicv5.c > +++ b/hw/intc/arm_gicv5.c > @@ -1040,7 +1040,15 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, > } > *data = v; > return true; > + case A_IRS_CR0: > + /* Enabling is instantaneous for us so IDLE is always 1 */ > + *data = cs->irs_cr0[domain] | R_IRS_CR0_IDLE_MASK; > + return true; > + case A_IRS_CR1: > + *data = cs->irs_cr1[domain]; > + return true; > } > + Trivial, but nicer to push that back to wherever this code first appeared (or drop it) > return false; > } From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89D101125847 for ; Wed, 11 Mar 2026 15:28:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0LUQ-0004Ep-Nr; Wed, 11 Mar 2026 11:28:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0LU5-000408-Ua; Wed, 11 Mar 2026 11:28:31 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0LU3-00046c-EB; Wed, 11 Mar 2026 11:28:29 -0400 Received: from mail.maildlp.com (unknown [172.18.224.150]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4fWF4r06nbzHnGcR; Wed, 11 Mar 2026 23:28:12 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id E6C1D4056A; Wed, 11 Mar 2026 23:28:19 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 11 Mar 2026 15:28:19 +0000 Date: Wed, 11 Mar 2026 15:28:18 +0000 To: Peter Maydell CC: , Subject: Re: [PATCH 28/65] hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1 Message-ID: <20260311152818.00004e4e@huawei.com> In-Reply-To: <20260223170212.441276-29-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> <20260223170212.441276-29-peter.maydell@linaro.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.15] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via qemu development Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 23 Feb 2026 17:01:35 +0000 Peter Maydell wrote: > The IRS_CR0 register has the main enable bit for the IRS, and an IDLE > bit to tell the guest when an enable/disable transition has > completed. > > The IRS_CR1 register has cacheability, shareability and cache hint > information to use for IRS memory accesses; since QEMU doesn't care > about this we can make it simply reads-as-written. > > Signed-off-by: Peter Maydell Trivial comment inline. Reviewed-by: Jonathan Cameron > --- > hw/intc/arm_gicv5.c | 14 ++++++++++++++ > hw/intc/arm_gicv5_common.c | 2 ++ > include/hw/intc/arm_gicv5_common.h | 2 ++ > 3 files changed, 18 insertions(+) > > diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c > index d1baa015d1..5f4c4158c4 100644 > --- a/hw/intc/arm_gicv5.c > +++ b/hw/intc/arm_gicv5.c > @@ -1040,7 +1040,15 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, > } > *data = v; > return true; > + case A_IRS_CR0: > + /* Enabling is instantaneous for us so IDLE is always 1 */ > + *data = cs->irs_cr0[domain] | R_IRS_CR0_IDLE_MASK; > + return true; > + case A_IRS_CR1: > + *data = cs->irs_cr1[domain]; > + return true; > } > + Trivial, but nicer to push that back to wherever this code first appeared (or drop it) > return false; > }