From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04ADD1125855 for ; Wed, 11 Mar 2026 16:41:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0Mcp-0002ce-Sa; Wed, 11 Mar 2026 12:41:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0McT-0002TZ-5q; Wed, 11 Mar 2026 12:41:19 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0McP-0003Xu-Ni; Wed, 11 Mar 2026 12:41:12 -0400 Received: from mail.maildlp.com (unknown [172.18.224.107]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4fWGhk2zGczHnGk2; Thu, 12 Mar 2026 00:40:54 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id 6BC2040589; Thu, 12 Mar 2026 00:41:02 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 11 Mar 2026 16:41:01 +0000 Date: Wed, 11 Mar 2026 16:41:00 +0000 To: Peter Maydell CC: , Subject: Re: [PATCH 40/65] target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1 Message-ID: <20260311164100.000057f3@huawei.com> In-Reply-To: <20260223170212.441276-41-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> <20260223170212.441276-41-peter.maydell@linaro.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.15] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Mon, 23 Feb 2026 17:01:47 +0000 Peter Maydell wrote: > The ICC_APR_EL1 GICv5 cpuif register records the physical active > priorities. Since the GICv5 always uses 5 bits of priority, this > register always has 32 non-RES0 bits, and we don't need the > complicated GICv3 setup where there might be 1, 2 or 4 APR registers. > > ICC_HAPR_EL1 is a read-only register which reports the current > running priority. This is defined to be the lowest set bit (i.e. > the highest priority) in the APR, or the Idle priority 0xff if there > are no active interrupts, so it is effectively a convenience > re-presentation of the APR register data. > > The APR register is banked per interrupt domain; ICC_APR_EL1 accesses > the version of the register corresponding to the current logical > interrupt domain. The APR data for the final domain (EL3) is > accessed via ICC_APR_EL3. Although we are starting with an EL1-only > implementation, we define the CPU state as banked here so we don't > have to change our representation of it later when we add EL3 and RME > support. > > Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCEC31125854 for ; Wed, 11 Mar 2026 16:42:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0Mcy-0002ds-0l; Wed, 11 Mar 2026 12:41:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0McT-0002TZ-5q; Wed, 11 Mar 2026 12:41:19 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0McP-0003Xu-Ni; Wed, 11 Mar 2026 12:41:12 -0400 Received: from mail.maildlp.com (unknown [172.18.224.107]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4fWGhk2zGczHnGk2; Thu, 12 Mar 2026 00:40:54 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id 6BC2040589; Thu, 12 Mar 2026 00:41:02 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 11 Mar 2026 16:41:01 +0000 Date: Wed, 11 Mar 2026 16:41:00 +0000 To: Peter Maydell CC: , Subject: Re: [PATCH 40/65] target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1 Message-ID: <20260311164100.000057f3@huawei.com> In-Reply-To: <20260223170212.441276-41-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> <20260223170212.441276-41-peter.maydell@linaro.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.15] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via qemu development Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 23 Feb 2026 17:01:47 +0000 Peter Maydell wrote: > The ICC_APR_EL1 GICv5 cpuif register records the physical active > priorities. Since the GICv5 always uses 5 bits of priority, this > register always has 32 non-RES0 bits, and we don't need the > complicated GICv3 setup where there might be 1, 2 or 4 APR registers. > > ICC_HAPR_EL1 is a read-only register which reports the current > running priority. This is defined to be the lowest set bit (i.e. > the highest priority) in the APR, or the Idle priority 0xff if there > are no active interrupts, so it is effectively a convenience > re-presentation of the APR register data. > > The APR register is banked per interrupt domain; ICC_APR_EL1 accesses > the version of the register corresponding to the current logical > interrupt domain. The APR data for the final domain (EL3) is > accessed via ICC_APR_EL3. Although we are starting with an EL1-only > implementation, we define the CPU state as banked here so we don't > have to change our representation of it later when we add EL3 and RME > support. > > Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron