From: Jason Gunthorpe <jgg@ziepe.ca>
To: Ankit Soni <Ankit.Soni@amd.com>
Cc: iommu@lists.linux.dev, vasant.hegde@amd.com,
suravee.suthikulpanit@amd.com, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/2] iommu/amd: Adhere to IVINFO[VASIZE] for address limits
Date: Thu, 12 Mar 2026 10:45:51 -0300 [thread overview]
Message-ID: <20260312134551.GL1469476@ziepe.ca> (raw)
In-Reply-To: <b1dc7207fbfc46d6bad89bc484d2034cd2bdd2db.1773058553.git.Ankit.Soni@amd.com>
On Mon, Mar 09, 2026 at 02:05:28PM +0000, Ankit Soni wrote:
> ACPI IVRS IVHD’s IVINFO field reports the maximum virtual address
> size (VASIZE) supported by the IOMMU. The AMD IOMMU driver currently
> caps this with pagetable level reported by EFR[HATS] when configuring
> paging domains (hw_max_vasz_lg2). On systems where firmware or VM
> advertises smaller or different limits, the driver may over-advertise
> capabilities and create domains outside the hardware’s actual bounds.
>
> Signed-off-by: Ankit Soni <Ankit.Soni@amd.com>
> ---
> drivers/iommu/amd/amd_iommu.h | 2 +-
> drivers/iommu/amd/amd_iommu_types.h | 1 +
> drivers/iommu/amd/init.c | 13 +++++++++----
> drivers/iommu/amd/iommu.c | 3 +--
> 4 files changed, 12 insertions(+), 7 deletions(-)
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Jason
prev parent reply other threads:[~2026-03-12 13:45 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-09 14:05 [PATCH v3 0/2] Respect VASIZE for address limits Ankit Soni
2026-03-09 14:05 ` [PATCH v3 1/2] iommu/amd: Remove PT_FEAT_DYNAMIC_TOP from PT_FORCE_ENABLED_FEATURES Ankit Soni
2026-03-11 16:24 ` Vasant Hegde
2026-03-11 16:44 ` Jason Gunthorpe
2026-03-12 4:10 ` Ankit Soni
2026-03-12 11:22 ` Jason Gunthorpe
2026-03-12 14:42 ` Ankit Soni
2026-03-09 14:05 ` [PATCH v3 2/2] iommu/amd: Adhere to IVINFO[VASIZE] for address limits Ankit Soni
2026-03-11 16:36 ` Vasant Hegde
2026-03-12 13:45 ` Jason Gunthorpe [this message]
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