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Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eduardo Habkost , Eric Blake , Markus Armbruster , Shameer Kolothum , Nicolin Chen , Matt Ochs , Nathan Chen Subject: [PATCH v2 0/8] hw/arm/smmuv3-accel: Support AUTO properties Date: Thu, 12 Mar 2026 14:03:19 -0700 Message-ID: <20260312210328.2016191-1-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BYAPR03CA0005.namprd03.prod.outlook.com (2603:10b6:a02:a8::18) To DS2PR12MB9567.namprd12.prod.outlook.com (2603:10b6:8:27c::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PR12MB9567:EE_|EAYPR12MB999156:EE_ X-MS-Office365-Filtering-Correlation-Id: a9e2168e-b217-471b-d940-08de807ad908 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|366016|1800799024|376014|7416014|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: MsiOiey67b/qHx6EkPgSr2pzRqKVcTB9aQiEKPmOu12ghnPR3P4zautcsRSbAwagAdit57SK0toNoqnk26k4CkbwrAhyArddT9yvB3AkccbQwenBhkPWU/bSCYMY/5SU2j8SZkj3Lk6AggXLk2drmF5zwK0sKEvKur9z1/hUEulVVmP7HHrXqApEj72gMoQdVC6R061Ezv4fLG36dBIuK8bZqvwVCsq5Ox2ahx9Wy6kEgxuN6HkRMIs8zaoHMCN+PxnHHbWGEK8ubXmsWOTy1SMY+W5IdthTtAs5LyZ/TDsnWFebdM8m7TG67QJ/za2FgAwxxpzNe22O2WaVdC9YAypUSzoVTrbE8cV3TpFHjU+X1g07FkPEsXJv/MRb3VCRCtV2aDVtQ/I/Efh/qfZG3PBmeBfKG9AVc97kVqHry4jBVD3gnhWqZdEctXD9NvM9D3MzjI7wXWWyQqWNc6I5pEPs0HsC7HsnnqnCdtCGzi4jt9zVckvbcmlbaCDvkINGAoFOOr7IznfLP0t+B59+gzEZSTwm94k2l1A8BldxNaGVMJgkc7DaQsZqCeTwLbrjFQPAkz786wOibk8aHo+et10L3bVVIUHwAg4OrrGqRlhDgU9SLA8qbmYU7O1Qh/Cgx5JMDtBjUjWkwjA5TjHsQUQvD4dzqzuQGJpLLE9PQXgbi/kBM4w+l/ulCg2dz8/Y X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi, This is a follow-up to the previous RFC series [0] that introduces support for specifying 'auto' for arm-smmuv3 accelerated mode's ATS, RIL, SSIDSIZE, and OAS feature properties. Based on feedback from the previous mailing list discussion, this refresh only converts the properties to the auto form, keeping the default values from Shameer's HW-accel SMMUv3 series [1]. A future series will introduce support for resolving the 'auto' values based on host SMMUv3 IDR values, as well as setting per-device ATS capability. When set to 'auto', RIL and OAS will use the defaults set from smmuv3_init_id_regs() while ATS and SSIDSIZE will remain at the initialized 0 value; i.e. RIL enabled, 44-bit OAS, ATS support disabled, 0-bit SSIDSIZE. A complete branch can be found here: https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-v2 Please take a look and let me know your feedback. Thanks, Nathan Changes from RFCv1: - Remove changes that resolve the 'auto' values based on host SMMUv3 - Restore defaults values for RIL, OAS, SSIDSIZE, and ATS - Update OasMode to accept all OAS sizes instead of only auto, 44, and 48 - Include comment in SsidSizeMode schema clarifying enum value ordering - Replace ats-enabled prop with a helper that accepts the dynamic casted TYPE_ARM_SMMUV3 object - Separate out guest vs. host ATS check in smmuv3_accel_check_hw_compatible() to a different commit - Document accel, RIL, OAS, SSIDSIZE, and ATS properties in qemu-options.hx Testing: Basic sanity testing was performed on an NVIDIA Grace platform with GPU device assignment and running CUDA test apps on the guest. Additional testing and feedback are welcome. [0] https://lore.kernel.org/qemu-devel/20260309192119.870186-1-nathanc@nvidia.com/ [1] https://lore.kernel.org/all/20260126104342.253965-1-skolothumtho@nvidia.com/ Nathan Chen (8): hw/arm/smmuv3-accel: Check ATS compatibility between host and guest hw/arm/smmuv3-accel: Change ATS property to OnOffAuto hw/arm/smmuv3-accel: Change RIL property to OnOffAuto qdev: Add a SsidSizeMode property hw/arm/smmuv3-accel: Change SSIDSIZE property to SsidSizeMode qdev: Add an OasMode property hw/arm/smmuv3-accel: Change OAS property to OasMode qemu-options.hx: Document arm-smmuv3 device's accel properties hw/arm/smmuv3-accel.c | 42 ++++++++++++++++++---- hw/arm/smmuv3.c | 38 ++++++++++---------- hw/arm/virt-acpi-build.c | 2 +- hw/core/qdev-properties-system.c | 27 +++++++++++++++ include/hw/arm/smmuv3.h | 11 +++--- include/hw/core/qdev-properties-system.h | 6 ++++ qapi/misc-arm.json | 44 ++++++++++++++++++++++++ qapi/pragma.json | 1 + qemu-options.hx | 29 +++++++++++++++- 9 files changed, 169 insertions(+), 31 deletions(-) -- 2.43.0