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Thu, 12 Mar 2026 19:18:55 -0700 (PDT) Received: from 192.168.0.29 ([2804:14d:4c71:86dd:588a:39d7:d008:37c2]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2beab3eec52sm796218eec.14.2026.03.12.19.18.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Mar 2026 19:18:54 -0700 (PDT) From: Lucas Amaral To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, agraf@csgraf.de, Lucas Amaral Subject: [PATCH v2 0/3] target/arm: ISV=0 data abort emulation library Date: Thu, 12 Mar 2026 23:18:47 -0300 Message-ID: <20260313021850.42379-1-lucaaamaral@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260309214852.92545-1-lucaaamaral@gmail.com> References: <20260309214852.92545-1-lucaaamaral@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::132f; envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x132f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_BARE_IP_2=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org When a guest triggers a data abort with ISV=0 (e.g. STP, LDP, SIMD/FP load/store, writeback addressing, atomics, exclusives), the ESR syndrome does not carry the access size or target register, so the hypervisor cannot emulate MMIO without decoding the faulting instruction. v1 handled this inside HVF with a hand-written decoder. Based on review feedback from Mohamed Mediouni and Peter Maydell, v2 restructures the implementation as: - A shared emulation library in target/arm/emulate/ with a decodetree decoder (a64-ldst.decode), usable by any hypervisor backend. - A callback-based interface (struct arm_emul_ops) that abstracts register and memory access, keeping the library hypervisor-agnostic. - HVF and WHPX backends wired as the first two consumers. Instruction classes handled (DDI 0487): - Load/store pair: STP, LDP, STNP, LDNP, STGP, LDPSW (C3.3.14-16) - SIMD/FP load/store pair and single (C3.3.10, C3.3.14-16) - All immediate addressing: unscaled, post/pre-index, unsigned offset - Register offset addressing with extend (C3.3.9) - Exclusives: STXR, LDXR, STXP, LDXP (C3.3.6) - Atomics: LDADD, LDCLR, LDEOR, LDSET, LDSMAX/MIN, LDUMAX/MIN, SWP - Compare-and-swap: CAS, CASP (C3.3.1) - LDRAA/LDRAB with FEAT_PAuth (C6.2.121) - PRFM, DC maintenance (as NOPs) Intentionally omitted (not observed in ISV=0 MMIO traps during testing): - AdvSIMD structure loads/stores (LD1/ST1 etc.) - MTE load/stores (FEAT_MTE) - 128-bit atomics (FEAT_LSE128) - MOPS (FEAT_MOPS) KVM NISV handling is a natural follow-up -- it requires similar arm_emul_ops callbacks using KVM vcpu ioctls. v1 -> v2: - Moved from HVF-specific inline decoder to shared library in target/arm/emulate/ (Mohamed Mediouni) - Added decodetree decoder for structured instruction parsing (Peter Maydell) - Made hypervisor-agnostic; wired HVF and WHPX (Peter Maydell) - Added CASP register-pair validation (odd/r31 -> UNHANDLED) - Added unit tests (19 test cases) - Split into 3 patches for reviewability Lucas Amaral (3): target/arm: add AArch64 ISV=0 instruction emulation library tests: add unit tests for ISV=0 emulation library target/arm: wire ISV=0 emulation into HVF and WHPX target/arm/emulate/a64-ldst.decode | 293 ++++++++++++ target/arm/emulate/arm_emulate.c | 738 +++++++++++++++++++++++++++++ target/arm/emulate/arm_emulate.h | 55 +++ target/arm/emulate/meson.build | 16 + target/arm/hvf/hvf.c | 94 +++- target/arm/meson.build | 1 + target/arm/whpx/whpx-all.c | 86 +++- tests/unit/meson.build | 1 + tests/unit/test-arm-emulate.c | 540 +++++++++++++++++++++ 9 files changed, 1820 insertions(+), 4 deletions(-) create mode 100644 target/arm/emulate/a64-ldst.decode create mode 100644 target/arm/emulate/arm_emulate.c create mode 100644 target/arm/emulate/arm_emulate.h create mode 100644 target/arm/emulate/meson.build create mode 100644 tests/unit/test-arm-emulate.c -- 2.52.0