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Sat, 14 Mar 2026 20:41:28 -0700 (PDT) Received: from 192.168.7.2 ([189.6.247.75]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2beab3eec8fsm8886424eec.13.2026.03.14.20.41.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 14 Mar 2026 20:41:28 -0700 (PDT) From: Lucas Amaral To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, agraf@csgraf.de, Lucas Amaral Subject: [PATCH v3 0/6] target/arm: ISV=0 data abort emulation library Date: Sun, 15 Mar 2026 00:41:17 -0300 Message-ID: <20260315034123.41921-1-lucaaamaral@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260313021850.42379-1-lucaaamaral@gmail.com> References: <20260313021850.42379-1-lucaaamaral@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1332; envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x1332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_BARE_IP_2=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add a shared emulation library for AArch64 load/store instructions that cause ISV=0 data aborts under hardware virtualization, and wire it into HVF (macOS) and WHPX (Windows). When the Instruction Syndrome Valid bit is clear, the hypervisor cannot determine the faulting instruction's target register or access size from the syndrome alone. This previously hit an assert(isv) and killed the VM. The library fetches and decodes the faulting instruction using a decodetree-generated decoder, then emulates it directly against the vCPU register file and memory. As suggested in v1 review, the library uses its own a64-ldst.decode rather than sharing target/arm/tcg/a64.decode. Beyond the practical complexity noted in review, the two have incompatible purposes: TCG's trans_* functions are a compiler — they emit IR ops into a translation block for later execution. This library's trans_* functions are an interpreter — they execute directly against the vCPU register file and memory. The decodetree-generated dispatcher calls trans_* by name, so both cannot coexist in the same translation unit. Decode patterns are kept consistent with TCG's where possible. This series wires the library into HVF (macOS) and WHPX (Windows). KVM on ARM already handles ISV=0 data aborts in-kernel via kvm_arm_handle_dabt_nisv(), but could use this library as a userspace fallback in the future. Changes since v2: - Split monolithic patch into 6 incremental patches: framework, then one patch per coherent instruction group (Peter) - Removed per-backend callback ops; library uses CPUArchState directly with cpu_memory_rw_debug() for memory access (Mohamed) - Removed mock unit tests (Mohamed; kvm-unit-tests is the right vehicle for decoder validation) - Added architectural justification for separate decode file Lucas Amaral (6): target/arm/emulate: add ISV=0 emulation library with load/store immediate target/arm/emulate: add load/store register offset target/arm/emulate: add load/store pair target/arm/emulate: add load/store exclusive target/arm/emulate: add atomic, compare-and-swap, and PAC load target/arm/hvf,whpx: wire ISV=0 emulation for data aborts target/arm/emulate/a64-ldst.decode | 293 +++++++++++ target/arm/emulate/arm_emulate.c | 747 +++++++++++++++++++++++++++++ target/arm/emulate/arm_emulate.h | 30 ++ target/arm/emulate/meson.build | 6 + target/arm/hvf/hvf.c | 41 +- target/arm/meson.build | 1 + target/arm/whpx/whpx-all.c | 39 +- 7 files changed, 1153 insertions(+), 4 deletions(-) create mode 100644 target/arm/emulate/a64-ldst.decode create mode 100644 target/arm/emulate/arm_emulate.c create mode 100644 target/arm/emulate/arm_emulate.h create mode 100644 target/arm/emulate/meson.build -- 2.52.0