From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 603B0F506CD for ; Mon, 16 Mar 2026 13:11:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w27fd-0000wm-GH; Mon, 16 Mar 2026 09:07:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w27fb-0000wI-Ou for qemu-arm@nongnu.org; Mon, 16 Mar 2026 09:07:43 -0400 Received: from p-west1-cluster3-host7-snip4-7.eps.apple.com ([57.103.66.50] helo=outbound.pv.icloud.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w27fZ-0003e7-Tz for qemu-arm@nongnu.org; Mon, 16 Mar 2026 09:07:43 -0400 Received: from outbound.pv.icloud.com (unknown [127.0.0.2]) by p00-icloudmta-asmtp-us-west-1a-100-percent-3 (Postfix) with ESMTPS id DAD261800371; Mon, 16 Mar 2026 13:07:39 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; t=1773666460; x=1776258460; bh=tLmmlXRu3wCud1P0iJWjv/5tKymKCqaSBnHRaVX0TfQ=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:x-icloud-hme; b=CXk3pD3j6xeSxA69+qUdW8AzWvqSBjP6m6kUzdUQAVDj2+yPRGGu5QMWCmMpYAjy9ikGZb7wixyIEBunRinPhr+OFfVnPgNw+qqN45+uCh7Rd+zsc8DRCX0eCkxl+AAok18IAk7M0tPGuniMKJ40bT0E09Wm7neA6laLVHlu9YBksp8P8GTVQGRPtz7IhKEUBufepplLsWsGtm+u0xn52HwwMWZowQY9YmWz41bcDPwNdOxoWvdhYvKm42TZTqus+XBiu2CYMKPzAHEY+gSUR9yz9mIwSNIPy1nS226mn9Xf6LgD0KC4H8QZTMBfAxk90DSDMBZyU2Znc3DhWlwgWA== mail-alias-created-date: 1752046281608 Received: from localhost.localdomain (unknown [17.56.9.36]) by p00-icloudmta-asmtp-us-west-1a-100-percent-3 (Postfix) with ESMTPSA id 654A61806D4B; Mon, 16 Mar 2026 13:07:14 +0000 (UTC) From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Marcel Apfelbaum , Yanan Wang , Zhao Liu , qemu-arm@nongnu.org, Peter Maydell , Roman Bolshakov , Alexander Graf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Eduardo Habkost , Phil Dennis-Jordan , Mohamed Mediouni Subject: [PATCH v20 10/15] hvf: sync registers used at EL2 Date: Mon, 16 Mar 2026 14:06:37 +0100 Message-ID: <20260316130642.13246-11-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260316130642.13246-1-mohamed@unpredictable.fr> References: <20260316130642.13246-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Info-Out: v=2.4 cv=UMTQ3Sfy c=1 sm=1 tr=0 ts=69b8009c cx=c_apl:c_pps:t_out a=azHRBMxVc17uSn+fyuI/eg==:117 a=azHRBMxVc17uSn+fyuI/eg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=Ml6fgdKjPmdD6r9HfocA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: UjkPfoeMEUK0dtJZyvrNiZxoDo4CYKOG X-Proofpoint-ORIG-GUID: UjkPfoeMEUK0dtJZyvrNiZxoDo4CYKOG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE2MDA5NyBTYWx0ZWRfX9vAfDAUezIjJ yG1okVCskQxq60XXU7eiABPuF4BdXw5eMVfc/gzliovzsth3yQLIpHV7ond6kMajnilyskvrnbL m3dTmSyPv4759tOn9V4l552HBGu3YTh441L1axagY9LLpRCMx2O/tUFDvco4xs3HxjWP7oNZQan iFXQ+dWgz7uM8Gbw0riy0hPbNnRr3485AKgmlsg3RSumM0iu/zQv/SvfZSaba5Hy5olcxk2PPfx luLSiktk8/9jIz2mndTRs6MLc0fV7mDACnTG7jQxxkoa2Nd0ejAgUA62PeXtDJqMnrTQQvQkrsc p4W6qof9GoA0r4MYOI9cx3cPPL7h8yZFLz72kXxaOOm5eOFSTah1iQXR6YFzIo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-16_04,2026-03-16_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 adultscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 clxscore=1030 lowpriorityscore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2603160097 Received-SPF: pass client-ip=57.103.66.50; envelope-from=mohamed@unpredictable.fr; helo=outbound.pv.icloud.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org When starting up the VM at EL2, more sysregs are available. Sync the state of those. In addition, sync the state of the EL1 physical timer when the vGIC is used, even if running at EL1. However, no OS running at EL1 is expected to use those registers. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daudé --- target/arm/hvf/hvf.c | 61 +++++++++++++++++++++++++++++++++---- target/arm/hvf/sysreg.c.inc | 44 ++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 6 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index c5f7682d7b..bf30285e74 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -467,37 +467,75 @@ static const struct hvf_reg_match hvf_sme2_preg_match[] = { * * SME2 registers are guarded by a runtime availability attribute instead of a * compile-time def, so verify those at runtime in hvf_arch_init_vcpu() below. + * + * Nested virt registers are handled via a runtime check, so override the guarded + * availability check done by Clang. */ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wunguarded-availability" + #define DEF_SYSREG(HVF_ID, ...) \ QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__))); #define DEF_SYSREG_15_02(...) +#define DEF_SYSREG_EL2(HVF_ID, ...) \ + QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__))); + +#define DEF_SYSREG_VGIC(HVF_ID, ...) \ + QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__))); + +#define DEF_SYSREG_VGIC_EL2(HVF_ID, ...) \ + QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__))); + #include "sysreg.c.inc" #undef DEF_SYSREG #undef DEF_SYSREG_15_02 +#undef DEF_SYSREG_EL2 +#undef DEF_SYSREG_VGIC +#undef DEF_SYSREG_VGIC_EL2 -#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID, +#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID}, #define DEF_SYSREG_15_02(...) +#define DEF_SYSREG_EL2(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, .el2 = true}, +#define DEF_SYSREG_VGIC(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, .vgic = true}, +#define DEF_SYSREG_VGIC_EL2(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, true, true}, + +struct hvf_sreg { + hv_sys_reg_t sreg; + bool vgic; + bool el2; +}; -static const hv_sys_reg_t hvf_sreg_list[] = { +static struct hvf_sreg hvf_sreg_list[] = { #include "sysreg.c.inc" }; #undef DEF_SYSREG #undef DEF_SYSREG_15_02 +#undef DEF_SYSREG_EL2 +#undef DEF_SYSREG_VGIC +#undef DEF_SYSREG_VGIC_EL2 + +#pragma clang diagnostic pop #define DEF_SYSREG(...) -#define DEF_SYSREG_15_02(HVF_ID, op0, op1, crn, crm, op2) HVF_ID, +#define DEF_SYSREG_15_02(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID}, +#define DEF_SYSREG_EL2(...) +#define DEF_SYSREG_VGIC(...) +#define DEF_SYSREG_VGIC_EL2(...) API_AVAILABLE(macos(15.2)) -static const hv_sys_reg_t hvf_sreg_list_sme2[] = { +static struct hvf_sreg hvf_sreg_list_sme2[] = { #include "sysreg.c.inc" }; #undef DEF_SYSREG #undef DEF_SYSREG_15_02 +#undef DEF_SYSREG_EL2 +#undef DEF_SYSREG_VGIC +#undef DEF_SYSREG_VGIC_EL2 /* * For FEAT_SME2 migration, we need to store PSTATE.{SM,ZA} bits which are @@ -1335,6 +1373,9 @@ int hvf_arch_init_vcpu(CPUState *cpu) #define DEF_SYSREG_15_02(HVF_ID, ...) \ g_assert(HVF_ID == KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__))); #define DEF_SYSREG(...) +#define DEF_SYSREG_EL2(...) +#define DEF_SYSREG_VGIC(...) +#define DEF_SYSREG_VGIC_EL2(...) #include "sysreg.c.inc" @@ -1362,11 +1403,19 @@ int hvf_arch_init_vcpu(CPUState *cpu) /* Populate cp list for all known sysregs */ for (i = 0; i < ARRAY_SIZE(hvf_sreg_list); i++) { - hv_sys_reg_t hvf_id = hvf_sreg_list[i]; + hv_sys_reg_t hvf_id = hvf_sreg_list[i].sreg; uint64_t kvm_id = HVF_TO_KVMID(hvf_id); uint32_t key = kvm_to_cpreg_id(kvm_id); const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); + if (hvf_sreg_list[i].vgic && !hvf_irqchip_in_kernel()) { + continue; + } + + if (hvf_sreg_list[i].el2 && !hvf_nested_virt_enabled()) { + continue; + } + if (ri) { assert(!(ri->type & ARM_CP_NO_RAW)); arm_cpu->cpreg_indexes[sregs_cnt++] = kvm_id; @@ -1375,7 +1424,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) if (__builtin_available(macOS 15.2, *)) { if (hvf_arm_sme2_supported()) { for (i = 0; i < ARRAY_SIZE(hvf_sreg_list_sme2); i++) { - hv_sys_reg_t hvf_id = hvf_sreg_list_sme2[i]; + hv_sys_reg_t hvf_id = hvf_sreg_list_sme2[i].sreg; uint64_t kvm_id = HVF_TO_KVMID(hvf_id); uint32_t key = kvm_to_cpreg_id(kvm_id); const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc index 7a2f880f78..c11dbf274e 100644 --- a/target/arm/hvf/sysreg.c.inc +++ b/target/arm/hvf/sysreg.c.inc @@ -153,3 +153,47 @@ DEF_SYSREG_15_02(HV_SYS_REG_ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF_SYSREG_15_02(HV_SYS_REG_ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) DEF_SYSREG_15_02(HV_SYS_REG_SMPRI_EL1, 3, 0, 1, 2, 4) DEF_SYSREG_15_02(HV_SYS_REG_SMCR_EL1, 3, 0, 1, 2, 6) +/* + * Block these because of the same issue as virtual counters in + * that caused the revert in 28b0ed32b32c7e5094cf2f1ec9c0645c65fad2aa + * + * DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_CTL_EL0, 3, 3, 14, 2, 1) + * DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_CVAL_EL0, 3, 3, 14, 2, 2) + */ +#ifdef SYNC_NO_RAW_REGS +DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_TVAL_EL0, 3, 3, 14, 2, 0) +#endif + +/* + * Also block these because of the same issue as virtual counters in + * that caused the revert in 28b0ed32b32c7e5094cf2f1ec9c0645c65fad2aa + * + * DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_CVAL_EL2, 3, 4, 14, 2, 2) + * DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_CTL_EL2, 3, 4, 14, 2, 1) + */ +DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHCTL_EL2, 3, 4, 14, 1, 0) +#ifdef SYNC_NO_RAW_REGS +DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_TVAL_EL2, 3, 4, 14, 2, 0) +#endif +DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTVOFF_EL2, 3, 4, 14, 0, 3) + +DEF_SYSREG_EL2(HV_SYS_REG_CPTR_EL2, 3, 4, 1, 1, 2) +DEF_SYSREG_EL2(HV_SYS_REG_ELR_EL2, 3, 4, 4, 0, 1) +DEF_SYSREG_EL2(HV_SYS_REG_ESR_EL2, 3, 4, 5, 2, 0) +DEF_SYSREG_EL2(HV_SYS_REG_FAR_EL2, 3, 4, 6, 0, 0) +DEF_SYSREG_EL2(HV_SYS_REG_HCR_EL2, 3, 4, 1, 1, 0) +DEF_SYSREG_EL2(HV_SYS_REG_HPFAR_EL2, 3, 4, 6, 0, 4) +DEF_SYSREG_EL2(HV_SYS_REG_MAIR_EL2, 3, 4, 10, 2, 0) +DEF_SYSREG_EL2(HV_SYS_REG_MDCR_EL2, 3, 4, 1, 1, 1) +DEF_SYSREG_EL2(HV_SYS_REG_SCTLR_EL2, 3, 4, 1, 0, 0) +DEF_SYSREG_EL2(HV_SYS_REG_SPSR_EL2, 3, 4, 4, 0, 0) +DEF_SYSREG_EL2(HV_SYS_REG_SP_EL2, 3, 6, 4, 1, 0) +DEF_SYSREG_EL2(HV_SYS_REG_TCR_EL2, 3, 4, 2, 0, 2) +DEF_SYSREG_EL2(HV_SYS_REG_TPIDR_EL2, 3, 4, 13, 0, 2) +DEF_SYSREG_EL2(HV_SYS_REG_TTBR0_EL2, 3, 4, 2, 0, 0) +DEF_SYSREG_EL2(HV_SYS_REG_TTBR1_EL2, 3, 4, 2, 0, 1) +DEF_SYSREG_EL2(HV_SYS_REG_VBAR_EL2, 3, 4, 12, 0, 0) +DEF_SYSREG_EL2(HV_SYS_REG_VMPIDR_EL2, 3, 4, 0, 0, 5) +DEF_SYSREG_EL2(HV_SYS_REG_VPIDR_EL2, 3, 4, 0, 0, 0) +DEF_SYSREG_EL2(HV_SYS_REG_VTCR_EL2, 3, 4, 2, 1, 2) +DEF_SYSREG_EL2(HV_SYS_REG_VTTBR_EL2, 3, 4, 2, 1, 0) -- 2.50.1 (Apple Git-155)