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[93.143.80.194]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-486f420de8asm56471095e9.3.2026.03.18.03.46.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 03:46:58 -0700 (PDT) From: Ruslan Ruslichenko To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, artem_mygaiev@epam.com, volodymyr_babchuk@epam.com, alex.bennee@linaro.org, peter.maydell@linaro.org, pierrick.bouvier@linaro.org, philmd@linaro.org, Ruslan_Ruslichenko@epam.com Subject: [RFC PATCH 1/9] target/arm: Add API for dynamic exception injection Date: Wed, 18 Mar 2026 11:46:32 +0100 Message-ID: <20260318104640.239752-2-ruslichenko.r@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318104640.239752-1-ruslichenko.r@gmail.com> References: <20260318104640.239752-1-ruslichenko.r@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=ruslichenko.r@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org From: Ruslan Ruslichenko Implement arm_cpu_inject_exception() to allow external clients, such as QEMU plugins or asynchronous timers, to inject exceptions into the ARM guest. Signed-off-by: Ruslan Ruslichenko --- target/arm/cpu.h | 4 ++++ target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 657ff4ab20..f1d2d6e240 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2680,4 +2680,8 @@ extern const uint64_t pred_esz_masks[5]; #define LOG2_TAG_GRANULE 4 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) +#ifndef CONFIG_USER_ONLY +void arm_cpu_inject_exception(int excp_index, uint32_t syndrome); +#endif + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 8c5769477c..73df3a9e6e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10241,4 +10241,59 @@ ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) return ARMSS_NonSecure; } } + +typedef struct { + int excp_index; + uint32_t syndrome; +} FIExcpAsync; + +static void fi_setup_exception(CPUState *cs, int excp_index, uint32_t syndrome) +{ + CPUARMState *env = cpu_env(cs); + + cs->exception_index = excp_index; + env->exception.syndrome = syndrome; + env->exception.vaddress = env->pc; + + if (excp_index == EXCP_VSERR) { + /* Serror syndrome constructed from vsesr_el2 */ + env->cp15.vsesr_el2 = syndrome; + } + + env->exception.target_el = arm_current_el(env); +} + +static void arm_cpu_inject_exception_async(CPUState *cs, run_on_cpu_data data) +{ + FIExcpAsync *excp_data = (FIExcpAsync *)data.host_ptr; + + fi_setup_exception(cs, excp_data->excp_index, excp_data->syndrome); + + g_free(excp_data); +} + +void arm_cpu_inject_exception(int excp_index, uint32_t syndrome) +{ + CPUState *cs = current_cpu; + + if (!cs) { + /* If we called outside CPU thread (timer callback, etc) schedule async */ + run_on_cpu_data async_data; + CPUState *cs0 = qemu_get_cpu(0); + + FIExcpAsync *excp_data = g_new0(FIExcpAsync, 1); + + excp_data->excp_index = excp_index; + excp_data->syndrome = syndrome; + + async_data.host_ptr = excp_data; + + async_run_on_cpu(cs0, arm_cpu_inject_exception_async, async_data); + return; + } + + fi_setup_exception(cs, excp_index, syndrome); + + cpu_loop_exit(cs); +} #endif /* !CONFIG_USER_ONLY */ -- 2.43.0