From: Nathan Chen <nathanc@nvidia.com>
To: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: "Eric Auger" <eric.auger@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Ani Sinha" <anisinha@redhat.com>,
"Shannon Zhao" <shannon.zhaosl@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>,
"Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Shameer Kolothum" <skolothumtho@nvidia.com>,
"Matt Ochs" <mochs@nvidia.com>,
"Nicolin Chen" <nicolinc@nvidia.com>,
"Nathan Chen" <nathanc@nvidia.com>
Subject: [PATCH v4 5/8] hw/arm/smmuv3-accel: Change SSIDSIZE property to SsidSizeMode
Date: Wed, 18 Mar 2026 11:49:04 -0700 [thread overview]
Message-ID: <20260318184907.4060030-6-nathanc@nvidia.com> (raw)
In-Reply-To: <20260318184907.4060030-1-nathanc@nvidia.com>
From: Nathan Chen <nathanc@nvidia.com>
Change accel SMMUv3 SSIDSIZE property from uint8_t to SsidSizeMode.
The 'auto' value is not implemented, as this commit is meant to set the
property to the correct type and avoid breaking JSON/QMP when the auto
mode is introduced. A future patch will implement resolution of 'auto'
value to match the host SMMUv3 SSIDSIZE value.
Fixes: b8c6f8a69d27 ("hw/arm/smmuv3-accel: Make SubstreamID support configurable")
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
hw/arm/smmuv3-accel.c | 23 +++++++++++++++++++++--
hw/arm/smmuv3.c | 19 ++++++++++---------
include/hw/arm/smmuv3-common.h | 1 -
include/hw/arm/smmuv3.h | 3 ++-
4 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index c31b64295e..bc6cbfebc2 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -802,7 +802,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)
SMMUState *bs = opaque;
SMMUv3State *s = ARM_SMMUV3(bs);
- if (s->ssidsize) {
+ if (s->ssidsize > SSID_SIZE_MODE_0) {
flags |= VIOMMU_FLAG_PASID_SUPPORTED;
}
return flags;
@@ -817,6 +817,22 @@ static const PCIIOMMUOps smmuv3_accel_ops = {
.get_msi_direct_gpa = smmuv3_accel_get_msi_gpa,
};
+/*
+ * This returns the value of a SsidSizeMode value offset by 1 to
+ * account for the enum values offset by 1 from actual values.
+ *
+ * SSID_SIZE_MODE_0 = 1, SSID_SIZE_MODE_1 = 2, etc. so return 0
+ * if SSID_SIZE_MODE_0 is passed as input, return 1 if
+ * SSID_SIZE_MODE_1 is passed as input, etc.
+ */
+static uint8_t ssidsize_mode_to_value(SsidSizeMode mode)
+{
+ if (mode == SSID_SIZE_MODE_AUTO) {
+ return 0;
+ }
+ return mode - 1;
+}
+
void smmuv3_accel_idr_override(SMMUv3State *s)
{
if (!s->accel) {
@@ -842,7 +858,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
* By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if user
* has enabled it.
*/
- s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize);
+ if (s->ssidsize > SSID_SIZE_MODE_0) {
+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE,
+ ssidsize_mode_to_value(s->ssidsize));
+ }
}
/* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index ea285bdf64..79018f8d66 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -20,6 +20,7 @@
#include "qemu/bitops.h"
#include "hw/core/irq.h"
#include "hw/core/sysbus.h"
+#include "hw/core/qdev-properties-system.h"
#include "migration/blocker.h"
#include "migration/vmstate.h"
#include "hw/core/qdev-properties.h"
@@ -625,7 +626,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
}
/* Multiple context descriptors require SubstreamID support */
- if (!s->ssidsize && STE_S1CDMAX(ste) != 0) {
+ if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) {
qemu_log_mask(LOG_UNIMP,
"SMMUv3: multiple S1 context descriptors require SubstreamID support. "
"Configure ssidsize > 0 (requires accel=on)\n");
@@ -1979,6 +1980,10 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
error_setg(errp, "ril auto mode is not supported");
return false;
}
+ if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
+ error_setg(errp, "ssidsize auto mode is not supported");
+ return false;
+ }
if (!s->accel) {
if (s->ril == ON_OFF_AUTO_OFF) {
@@ -1993,7 +1998,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
error_setg(errp, "OAS must be 44 bits when accel=off");
return false;
}
- if (s->ssidsize) {
+ if (s->ssidsize > SSID_SIZE_MODE_0) {
error_setg(errp, "ssidsize can only be set if accel=on");
return false;
}
@@ -2011,11 +2016,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
error_setg(errp, "OAS can only be set to 44 or 48 bits");
return false;
}
- if (s->ssidsize > SMMU_SSID_MAX_BITS) {
- error_setg(errp, "ssidsize must be in the range 0 to %d",
- SMMU_SSID_MAX_BITS);
- return false;
- }
return true;
}
@@ -2144,7 +2144,8 @@ static const Property smmuv3_properties[] = {
DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON),
DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF),
DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
- DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0),
+ DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize,
+ SSID_SIZE_MODE_0),
};
static void smmuv3_instance_init(Object *obj)
@@ -2185,7 +2186,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
"A value of N allows SSIDs in the range [0 .. 2^N - 1]. "
"Valid range is 0-20, where 0 disables SubstreamID support. "
"Defaults to 0. A value greater than 0 is required to enable "
- "PASID support.");
+ "PASID support. ssidsize=auto is not supported.");
}
static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,
diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h
index 9f78bbe89e..7f0f992dfd 100644
--- a/include/hw/arm/smmuv3-common.h
+++ b/include/hw/arm/smmuv3-common.h
@@ -311,7 +311,6 @@ REG32(IDR1, 0x4)
FIELD(IDR1, TABLES_PRESET, 30, 1)
FIELD(IDR1, ECMDQ, 31, 1)
-#define SMMU_SSID_MAX_BITS 20
#define SMMU_IDR1_SIDSIZE 16
#define SMMU_CMDQS 19
#define SMMU_EVENTQS 19
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index c35e599bbc..ddf472493d 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -21,6 +21,7 @@
#include "hw/arm/smmu-common.h"
#include "qom/object.h"
+#include "qapi/qapi-types-misc-arm.h"
#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
@@ -72,7 +73,7 @@ struct SMMUv3State {
OnOffAuto ril;
OnOffAuto ats;
uint8_t oas;
- uint8_t ssidsize;
+ SsidSizeMode ssidsize;
};
typedef enum {
--
2.43.0
next prev parent reply other threads:[~2026-03-18 18:51 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-18 18:48 [PATCH for-11.0 v4 0/8] hw/arm/smmuv3-accel: Support AUTO properties Nathan Chen
2026-03-18 18:49 ` [PATCH v4 1/8] hw/arm/smmuv3-accel: Check ATS compatibility between host and guest Nathan Chen
2026-03-18 18:49 ` [PATCH v4 2/8] hw/arm/smmuv3-accel: Change ATS property to OnOffAuto Nathan Chen
2026-03-19 8:10 ` Shameer Kolothum Thodi
2026-03-19 9:35 ` Eric Auger
2026-03-19 11:54 ` Markus Armbruster
2026-03-18 18:49 ` [PATCH v4 3/8] hw/arm/smmuv3-accel: Change RIL " Nathan Chen
2026-03-19 8:12 ` Shameer Kolothum Thodi
2026-03-19 9:37 ` Eric Auger
2026-03-19 11:55 ` Markus Armbruster
2026-03-18 18:49 ` [PATCH v4 4/8] qdev: Add a SsidSizeMode property Nathan Chen
2026-03-19 12:02 ` Markus Armbruster
2026-03-19 12:08 ` Markus Armbruster
2026-03-18 18:49 ` Nathan Chen [this message]
2026-03-19 8:35 ` [PATCH v4 5/8] hw/arm/smmuv3-accel: Change SSIDSIZE property to SsidSizeMode Shameer Kolothum Thodi
2026-03-19 9:48 ` Eric Auger
2026-03-19 12:14 ` Markus Armbruster
2026-03-23 17:28 ` Nathan Chen
2026-03-23 17:41 ` Shameer Kolothum Thodi
2026-03-24 5:39 ` Markus Armbruster
2026-03-23 17:41 ` Eric Auger
2026-03-18 18:49 ` [PATCH v4 6/8] qdev: Add an OasMode property Nathan Chen
2026-03-19 12:16 ` Markus Armbruster
2026-03-18 18:49 ` [PATCH v4 7/8] hw/arm/smmuv3-accel: Change OAS property to OasMode Nathan Chen
2026-03-19 8:39 ` Shameer Kolothum Thodi
2026-03-19 9:51 ` Eric Auger
2026-03-19 12:20 ` Markus Armbruster
2026-03-19 16:57 ` Nathan Chen
2026-03-20 7:53 ` Markus Armbruster
2026-03-23 17:47 ` Nathan Chen
2026-03-18 18:49 ` [PATCH v4 8/8] qemu-options.hx: Document arm-smmuv3 device's accel properties Nathan Chen
2026-03-19 12:21 ` Markus Armbruster
2026-03-19 17:07 ` Nathan Chen
2026-03-19 10:01 ` [PATCH for-11.0 v4 0/8] hw/arm/smmuv3-accel: Support AUTO properties Eric Auger
2026-03-19 10:15 ` Shameer Kolothum Thodi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260318184907.4060030-6-nathanc@nvidia.com \
--to=nathanc@nvidia.com \
--cc=anisinha@redhat.com \
--cc=armbru@redhat.com \
--cc=berrange@redhat.com \
--cc=eblake@redhat.com \
--cc=eric.auger@redhat.com \
--cc=imammedo@redhat.com \
--cc=mochs@nvidia.com \
--cc=mst@redhat.com \
--cc=nicolinc@nvidia.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=shannon.zhaosl@gmail.com \
--cc=skolothumtho@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.