diff for duplicates of <20260319101911.31348-1-midgy971@gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index e5e30bb..005e632 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,43 +1,48 @@
-On 2026/03/04, Shawn Lin wrote:\r
-> IIUC, you are using Claude to help generate this patch, please\r
-> describe it properly, for example,\r
->\r
-> Co-developed-by: Claude claude-opus-4-20250514 [1]\r
-> or\r
-> Assisted-by: Claude:claude-3-opus [2]\r
->\r
-> [1] https://lwn.net/Articles/1031473/\r
-> [2] https://docs.kernel.org/process/coding-assistants.html\r
-\r
-Thank you for the guidance. I used Claude as a coding assistant and\r
-will use the proper tag in v3:\r
-\r
-  Assisted-by: Claude:claude-3-opus\r
-  Signed-off-by: MidG971 <midgy971@gmail.com>\r
-\r
-> There is a missing pipe clock which should be fixed. Please\r
-> refer to David's patch[3].\r
->\r
-> [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1\r
-\r
-Since our board-level &pcie3x2 override replaces the clocks property\r
-entirely, v3 adds CLK_PCIE30X2_PIPE_DFT ("pipe") as well, consistent\r
-with David's base DTS patch.\r
-\r
-I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes\r
-successfully and the NVMe device is detected at 15.75 Gb/s. The\r
-pcie30_refclk clock appears in the clock tree at 100MHz with pcie3x2\r
-as its consumer.\r
-\r
-One note on the pipe clock test: CLK_PCIE30X2_PIPE_DFT is defined in\r
-rk3568-cru.h but was not yet registered in the CRU driver in the\r
-tested kernel build, so the pipe clock was excluded from the\r
-functional test (pcie3x2 probe fails with -ENOENT at clock index 5\r
-when it is included). The gated-fixed-clock node and ref clock were\r
-verified working. I expect the pipe clock will work once the CRU\r
-driver registers it alongside David's DTS patch.\r
-\r
-v3 is sent separately.\r
-\r
-Best regards,\r
+On 2026/03/04, Shawn Lin wrote:
+> IIUC, you are using Claude to help generate this patch, please
+> describe it properly, for example,
+>
+> Co-developed-by: Claude claude-opus-4-20250514 [1]
+> or
+> Assisted-by: Claude:claude-3-opus [2]
+>
+> [1] https://lwn.net/Articles/1031473/
+> [2] https://docs.kernel.org/process/coding-assistants.html
+
+Thank you for the guidance. I used Claude as a coding assistant and
+will use the proper tag in v3:
+
+  Assisted-by: Claude:claude-3-opus
+  Signed-off-by: MidG971 <midgy971@gmail.com>
+
+> There is a missing pipe clock which should be fixed. Please
+> refer to David's patch[3].
+>
+> [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
+
+Since our board-level &pcie3x2 override replaces the clocks property
+entirely, v3 adds CLK_PCIE30X2_PIPE_DFT ("pipe") as well, consistent
+with David's base DTS patch.
+
+I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes
+successfully and the NVMe device is detected at 15.75 Gb/s. The
+pcie30_refclk clock appears in the clock tree at 100MHz with pcie3x2
+as its consumer.
+
+One note on the pipe clock test: CLK_PCIE30X2_PIPE_DFT is defined in
+rk3568-cru.h but was not yet registered in the CRU driver in the
+tested kernel build, so the pipe clock was excluded from the
+functional test (pcie3x2 probe fails with -ENOENT at clock index 5
+when it is included). The gated-fixed-clock node and ref clock were
+verified working. I expect the pipe clock will work once the CRU
+driver registers it alongside David's DTS patch.
+
+v3 is sent separately.
+
+Best regards,
 MidG971
+
+_______________________________________________
+Linux-rockchip mailing list
+Linux-rockchip@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-rockchip
diff --git a/a/content_digest b/N1/content_digest
index f742e0d..274164e 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -11,48 +11,53 @@
  " jonas@kwiboo.se\0"
  "\00:1\0"
  "b\0"
- "On 2026/03/04, Shawn Lin wrote:\r\n"
- "> IIUC, you are using Claude to help generate this patch, please\r\n"
- "> describe it properly, for example,\r\n"
- ">\r\n"
- "> Co-developed-by: Claude claude-opus-4-20250514 [1]\r\n"
- "> or\r\n"
- "> Assisted-by: Claude:claude-3-opus [2]\r\n"
- ">\r\n"
- "> [1] https://lwn.net/Articles/1031473/\r\n"
- "> [2] https://docs.kernel.org/process/coding-assistants.html\r\n"
- "\r\n"
- "Thank you for the guidance. I used Claude as a coding assistant and\r\n"
- "will use the proper tag in v3:\r\n"
- "\r\n"
- "  Assisted-by: Claude:claude-3-opus\r\n"
- "  Signed-off-by: MidG971 <midgy971@gmail.com>\r\n"
- "\r\n"
- "> There is a missing pipe clock which should be fixed. Please\r\n"
- "> refer to David's patch[3].\r\n"
- ">\r\n"
- "> [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1\r\n"
- "\r\n"
- "Since our board-level &pcie3x2 override replaces the clocks property\r\n"
- "entirely, v3 adds CLK_PCIE30X2_PIPE_DFT (\"pipe\") as well, consistent\r\n"
- "with David's base DTS patch.\r\n"
- "\r\n"
- "I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes\r\n"
- "successfully and the NVMe device is detected at 15.75 Gb/s. The\r\n"
- "pcie30_refclk clock appears in the clock tree at 100MHz with pcie3x2\r\n"
- "as its consumer.\r\n"
- "\r\n"
- "One note on the pipe clock test: CLK_PCIE30X2_PIPE_DFT is defined in\r\n"
- "rk3568-cru.h but was not yet registered in the CRU driver in the\r\n"
- "tested kernel build, so the pipe clock was excluded from the\r\n"
- "functional test (pcie3x2 probe fails with -ENOENT at clock index 5\r\n"
- "when it is included). The gated-fixed-clock node and ref clock were\r\n"
- "verified working. I expect the pipe clock will work once the CRU\r\n"
- "driver registers it alongside David's DTS patch.\r\n"
- "\r\n"
- "v3 is sent separately.\r\n"
- "\r\n"
- "Best regards,\r\n"
- MidG971
+ "On 2026/03/04, Shawn Lin wrote:\n"
+ "> IIUC, you are using Claude to help generate this patch, please\n"
+ "> describe it properly, for example,\n"
+ ">\n"
+ "> Co-developed-by: Claude claude-opus-4-20250514 [1]\n"
+ "> or\n"
+ "> Assisted-by: Claude:claude-3-opus [2]\n"
+ ">\n"
+ "> [1] https://lwn.net/Articles/1031473/\n"
+ "> [2] https://docs.kernel.org/process/coding-assistants.html\n"
+ "\n"
+ "Thank you for the guidance. I used Claude as a coding assistant and\n"
+ "will use the proper tag in v3:\n"
+ "\n"
+ "  Assisted-by: Claude:claude-3-opus\n"
+ "  Signed-off-by: MidG971 <midgy971@gmail.com>\n"
+ "\n"
+ "> There is a missing pipe clock which should be fixed. Please\n"
+ "> refer to David's patch[3].\n"
+ ">\n"
+ "> [3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1\n"
+ "\n"
+ "Since our board-level &pcie3x2 override replaces the clocks property\n"
+ "entirely, v3 adds CLK_PCIE30X2_PIPE_DFT (\"pipe\") as well, consistent\n"
+ "with David's base DTS patch.\n"
+ "\n"
+ "I tested v3 on the ROCK 3B (kernel 6.19.0-rc5): pcie3x2 probes\n"
+ "successfully and the NVMe device is detected at 15.75 Gb/s. The\n"
+ "pcie30_refclk clock appears in the clock tree at 100MHz with pcie3x2\n"
+ "as its consumer.\n"
+ "\n"
+ "One note on the pipe clock test: CLK_PCIE30X2_PIPE_DFT is defined in\n"
+ "rk3568-cru.h but was not yet registered in the CRU driver in the\n"
+ "tested kernel build, so the pipe clock was excluded from the\n"
+ "functional test (pcie3x2 probe fails with -ENOENT at clock index 5\n"
+ "when it is included). The gated-fixed-clock node and ref clock were\n"
+ "verified working. I expect the pipe clock will work once the CRU\n"
+ "driver registers it alongside David's DTS patch.\n"
+ "\n"
+ "v3 is sent separately.\n"
+ "\n"
+ "Best regards,\n"
+ "MidG971\n"
+ "\n"
+ "_______________________________________________\n"
+ "Linux-rockchip mailing list\n"
+ "Linux-rockchip@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-rockchip
 
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+5d271b4e942b8554ffbfd49a5067c0074dbc73f710377a9e908235b979db9302
