diff for duplicates of <20260319145120.99833-1-midgy971@gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index 661fb39..b6f2e42 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,83 +1,89 @@
-The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to\r
-provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.\r
-This chip is currently modeled only as a fixed regulator\r
-(vcc3v3_pi6c_03), with no clock output representation.\r
-\r
-The PI6C20100 is a clock generator, not a power supply. Model it\r
-properly as a gated-fixed-clock, following the pattern established\r
-for the Rock 5 ITX and other boards with similar PCIe clock buffer\r
-chips.\r
-\r
-The regulator node is kept as-is since it controls the power supply\r
-to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node\r
-references this regulator as its vdd-supply and provides a proper\r
-100MHz clock output. The pcie3x2 node is updated to include the\r
-pipe and reference clocks, matching the approach used in\r
-rk3588-rock-5-itx.dts.\r
-\r
-Assisted-by: Claude:claude-3-opus\r
-Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>\r
-Signed-off-by: Midgy BALON <midgy971@gmail.com>\r
----\r
-\r
-Changes since v3 [1]:\r
- - Add Reviewed-by from Shawn Lin\r
-\r
-Changes since v2 [2]:\r
- - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)\r
- - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks\r
-   override (Shawn, referencing David's patch [3])\r
-\r
-Changes since v1 [4]:\r
- - Drop phy-supply approach entirely (Jonas, Shawn)\r
- - Model PI6C20100 as gated-fixed-clock instead\r
- - Wire reference clock to pcie3x2 controller\r
- - Follow pattern from rk3588-rock-5-itx.dts\r
-\r
-[1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/\r
-[2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/\r
-[3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1\r
-[4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/\r
-\r
- arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-\r
- 1 file changed, 20 insertions(+), 1 deletion(-)\r
-\r
-diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\r
-index c5f67dd6dfd9..1a2b3c4d5e6f 100644\r
---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\r
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\r
-@@ -56,7 +56,16 @@\r
- 		};\r
- 	};\r
-\r
--	/* pi6c pcie clock generator */\r
-+	/* PI6C20100 PCIe reference clock buffer (100MHz) */\r
-+	pcie30_refclk: pcie-clock-generator {\r
-+		compatible = "gated-fixed-clock";\r
-+		#clock-cells = <0>;\r
-+		clock-frequency = <100000000>;\r
-+		clock-output-names = "pcie30_refclk";\r
-+		vdd-supply = <&vcc3v3_pi6c_03>;\r
-+	};\r
-+\r
-+	/* PI6C20100 power supply - active-high GPIO0_D4 */\r
- 	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {\r
- 		compatible = "regulator-fixed";\r
- 		enable-active-high;\r
-@@ -553,6 +562,15 @@\r
- };\r
-\r
- &pcie3x2 {\r
-+	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,\r
-+		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,\r
-+		 <&cru CLK_PCIE30X2_AUX_NDFT>,\r
-+		 <&cru CLK_PCIE30X2_PIPE_DFT>,\r
-+		 <&pcie30_refclk>;\r
-+	clock-names = "aclk_mst", "aclk_slv",\r
-+		      "aclk_dbi", "pclk", "aux",\r
-+		      "pipe", "ref";\r
- 	pinctrl-names = "default";\r
- 	pinctrl-0 = <&pcie30x2m1_pins>;\r
- 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;\r
---\r
+The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
+provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
+This chip is currently modeled only as a fixed regulator
+(vcc3v3_pi6c_03), with no clock output representation.
+
+The PI6C20100 is a clock generator, not a power supply. Model it
+properly as a gated-fixed-clock, following the pattern established
+for the Rock 5 ITX and other boards with similar PCIe clock buffer
+chips.
+
+The regulator node is kept as-is since it controls the power supply
+to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node
+references this regulator as its vdd-supply and provides a proper
+100MHz clock output. The pcie3x2 node is updated to include the
+pipe and reference clocks, matching the approach used in
+rk3588-rock-5-itx.dts.
+
+Assisted-by: Claude:claude-3-opus
+Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Midgy BALON <midgy971@gmail.com>
+---
+
+Changes since v3 [1]:
+ - Add Reviewed-by from Shawn Lin
+
+Changes since v2 [2]:
+ - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)
+ - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks
+   override (Shawn, referencing David's patch [3])
+
+Changes since v1 [4]:
+ - Drop phy-supply approach entirely (Jonas, Shawn)
+ - Model PI6C20100 as gated-fixed-clock instead
+ - Wire reference clock to pcie3x2 controller
+ - Follow pattern from rk3588-rock-5-itx.dts
+
+[1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
+[2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/
+[3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1
+[4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/
+
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+index c5f67dd6dfd9..1a2b3c4d5e6f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+@@ -56,7 +56,16 @@
+ 		};
+ 	};
+
+-	/* pi6c pcie clock generator */
++	/* PI6C20100 PCIe reference clock buffer (100MHz) */
++	pcie30_refclk: pcie-clock-generator {
++		compatible = "gated-fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <100000000>;
++		clock-output-names = "pcie30_refclk";
++		vdd-supply = <&vcc3v3_pi6c_03>;
++	};
++
++	/* PI6C20100 power supply - active-high GPIO0_D4 */
+ 	vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -553,6 +562,15 @@
+ };
+
+ &pcie3x2 {
++	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
++		 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
++		 <&cru CLK_PCIE30X2_AUX_NDFT>,
++		 <&cru CLK_PCIE30X2_PIPE_DFT>,
++		 <&pcie30_refclk>;
++	clock-names = "aclk_mst", "aclk_slv",
++		      "aclk_dbi", "pclk", "aux",
++		      "pipe", "ref";
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pcie30x2m1_pins>;
+ 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+--
 2.39.5
+
+
+_______________________________________________
+Linux-rockchip mailing list
+Linux-rockchip@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-rockchip
diff --git a/a/content_digest b/N1/content_digest
index 6baad0a..61627c6 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -11,88 +11,94 @@
  " MidG971 <midgy971@gmail.com>\0"
  "\00:1\0"
  "b\0"
- "The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to\r\n"
- "provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.\r\n"
- "This chip is currently modeled only as a fixed regulator\r\n"
- "(vcc3v3_pi6c_03), with no clock output representation.\r\n"
- "\r\n"
- "The PI6C20100 is a clock generator, not a power supply. Model it\r\n"
- "properly as a gated-fixed-clock, following the pattern established\r\n"
- "for the Rock 5 ITX and other boards with similar PCIe clock buffer\r\n"
- "chips.\r\n"
- "\r\n"
- "The regulator node is kept as-is since it controls the power supply\r\n"
- "to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node\r\n"
- "references this regulator as its vdd-supply and provides a proper\r\n"
- "100MHz clock output. The pcie3x2 node is updated to include the\r\n"
- "pipe and reference clocks, matching the approach used in\r\n"
- "rk3588-rock-5-itx.dts.\r\n"
- "\r\n"
- "Assisted-by: Claude:claude-3-opus\r\n"
- "Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>\r\n"
- "Signed-off-by: Midgy BALON <midgy971@gmail.com>\r\n"
- "---\r\n"
- "\r\n"
- "Changes since v3 [1]:\r\n"
- " - Add Reviewed-by from Shawn Lin\r\n"
- "\r\n"
- "Changes since v2 [2]:\r\n"
- " - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)\r\n"
- " - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks\r\n"
- "   override (Shawn, referencing David's patch [3])\r\n"
- "\r\n"
- "Changes since v1 [4]:\r\n"
- " - Drop phy-supply approach entirely (Jonas, Shawn)\r\n"
- " - Model PI6C20100 as gated-fixed-clock instead\r\n"
- " - Wire reference clock to pcie3x2 controller\r\n"
- " - Follow pattern from rk3588-rock-5-itx.dts\r\n"
- "\r\n"
- "[1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/\r\n"
- "[2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/\r\n"
- "[3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1\r\n"
- "[4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/\r\n"
- "\r\n"
- " arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-\r\n"
- " 1 file changed, 20 insertions(+), 1 deletion(-)\r\n"
- "\r\n"
- "diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\r\n"
- "index c5f67dd6dfd9..1a2b3c4d5e6f 100644\r\n"
- "--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\r\n"
- "+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\r\n"
- "@@ -56,7 +56,16 @@\r\n"
- " \t\t};\r\n"
- " \t};\r\n"
- "\r\n"
- "-\t/* pi6c pcie clock generator */\r\n"
- "+\t/* PI6C20100 PCIe reference clock buffer (100MHz) */\r\n"
- "+\tpcie30_refclk: pcie-clock-generator {\r\n"
- "+\t\tcompatible = \"gated-fixed-clock\";\r\n"
- "+\t\t#clock-cells = <0>;\r\n"
- "+\t\tclock-frequency = <100000000>;\r\n"
- "+\t\tclock-output-names = \"pcie30_refclk\";\r\n"
- "+\t\tvdd-supply = <&vcc3v3_pi6c_03>;\r\n"
- "+\t};\r\n"
- "+\r\n"
- "+\t/* PI6C20100 power supply - active-high GPIO0_D4 */\r\n"
- " \tvcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {\r\n"
- " \t\tcompatible = \"regulator-fixed\";\r\n"
- " \t\tenable-active-high;\r\n"
- "@@ -553,6 +562,15 @@\r\n"
- " };\r\n"
- "\r\n"
- " &pcie3x2 {\r\n"
- "+\tclocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,\r\n"
- "+\t\t <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,\r\n"
- "+\t\t <&cru CLK_PCIE30X2_AUX_NDFT>,\r\n"
- "+\t\t <&cru CLK_PCIE30X2_PIPE_DFT>,\r\n"
- "+\t\t <&pcie30_refclk>;\r\n"
- "+\tclock-names = \"aclk_mst\", \"aclk_slv\",\r\n"
- "+\t\t      \"aclk_dbi\", \"pclk\", \"aux\",\r\n"
- "+\t\t      \"pipe\", \"ref\";\r\n"
- " \tpinctrl-names = \"default\";\r\n"
- " \tpinctrl-0 = <&pcie30x2m1_pins>;\r\n"
- " \treset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;\r\n"
- "--\r\n"
- 2.39.5
+ "The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to\n"
+ "provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.\n"
+ "This chip is currently modeled only as a fixed regulator\n"
+ "(vcc3v3_pi6c_03), with no clock output representation.\n"
+ "\n"
+ "The PI6C20100 is a clock generator, not a power supply. Model it\n"
+ "properly as a gated-fixed-clock, following the pattern established\n"
+ "for the Rock 5 ITX and other boards with similar PCIe clock buffer\n"
+ "chips.\n"
+ "\n"
+ "The regulator node is kept as-is since it controls the power supply\n"
+ "to the PI6C20100 chip via GPIO0_D4. The new gated-fixed-clock node\n"
+ "references this regulator as its vdd-supply and provides a proper\n"
+ "100MHz clock output. The pcie3x2 node is updated to include the\n"
+ "pipe and reference clocks, matching the approach used in\n"
+ "rk3588-rock-5-itx.dts.\n"
+ "\n"
+ "Assisted-by: Claude:claude-3-opus\n"
+ "Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>\n"
+ "Signed-off-by: Midgy BALON <midgy971@gmail.com>\n"
+ "---\n"
+ "\n"
+ "Changes since v3 [1]:\n"
+ " - Add Reviewed-by from Shawn Lin\n"
+ "\n"
+ "Changes since v2 [2]:\n"
+ " - Fix AI attribution: use Assisted-by tag instead of Signed-off-by (Shawn)\n"
+ " - Add missing pipe clock (CLK_PCIE30X2_PIPE_DFT) to pcie3x2 clocks\n"
+ "   override (Shawn, referencing David's patch [3])\n"
+ "\n"
+ "Changes since v1 [4]:\n"
+ " - Drop phy-supply approach entirely (Jonas, Shawn)\n"
+ " - Model PI6C20100 as gated-fixed-clock instead\n"
+ " - Wire reference clock to pcie3x2 controller\n"
+ " - Follow pattern from rk3588-rock-5-itx.dts\n"
+ "\n"
+ "[1] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/\n"
+ "[2] https://lore.kernel.org/linux-rockchip/20260304132957.684616-1-midgy971@gmail.com/\n"
+ "[3] https://lore.kernel.org/linux-rockchip/d981fa84-bd05-ac9d-98ca-89ee47177829@rock-chips.com/T/#m6a8289609e6a60691d3c06358b6322c7aa5e43d1\n"
+ "[4] https://lore.kernel.org/linux-rockchip/20260213151452.535527-1-midgy971@gmail.com/\n"
+ "\n"
+ " arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 21 ++++++++++++++++++++-\n"
+ " 1 file changed, 20 insertions(+), 1 deletion(-)\n"
+ "\n"
+ "diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\n"
+ "index c5f67dd6dfd9..1a2b3c4d5e6f 100644\n"
+ "--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\n"
+ "+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts\n"
+ "@@ -56,7 +56,16 @@\n"
+ " \t\t};\n"
+ " \t};\n"
+ "\n"
+ "-\t/* pi6c pcie clock generator */\n"
+ "+\t/* PI6C20100 PCIe reference clock buffer (100MHz) */\n"
+ "+\tpcie30_refclk: pcie-clock-generator {\n"
+ "+\t\tcompatible = \"gated-fixed-clock\";\n"
+ "+\t\t#clock-cells = <0>;\n"
+ "+\t\tclock-frequency = <100000000>;\n"
+ "+\t\tclock-output-names = \"pcie30_refclk\";\n"
+ "+\t\tvdd-supply = <&vcc3v3_pi6c_03>;\n"
+ "+\t};\n"
+ "+\n"
+ "+\t/* PI6C20100 power supply - active-high GPIO0_D4 */\n"
+ " \tvcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {\n"
+ " \t\tcompatible = \"regulator-fixed\";\n"
+ " \t\tenable-active-high;\n"
+ "@@ -553,6 +562,15 @@\n"
+ " };\n"
+ "\n"
+ " &pcie3x2 {\n"
+ "+\tclocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,\n"
+ "+\t\t <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,\n"
+ "+\t\t <&cru CLK_PCIE30X2_AUX_NDFT>,\n"
+ "+\t\t <&cru CLK_PCIE30X2_PIPE_DFT>,\n"
+ "+\t\t <&pcie30_refclk>;\n"
+ "+\tclock-names = \"aclk_mst\", \"aclk_slv\",\n"
+ "+\t\t      \"aclk_dbi\", \"pclk\", \"aux\",\n"
+ "+\t\t      \"pipe\", \"ref\";\n"
+ " \tpinctrl-names = \"default\";\n"
+ " \tpinctrl-0 = <&pcie30x2m1_pins>;\n"
+ " \treset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;\n"
+ "--\n"
+ "2.39.5\n"
+ "\n"
+ "\n"
+ "_______________________________________________\n"
+ "Linux-rockchip mailing list\n"
+ "Linux-rockchip@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-rockchip
 
-913b38d6953f7ec1b4a4ed7a558787afb374ea9b09c118cd6c14c1ac17574a98
+bc663a92f48ef657e90d326ed0e26fab211e80071fbf99ce48906294ee203beb
