From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oupton@kernel.org>,
Zenghui Yu <yuzenghui@huawei.com>,
Sascha Bischoff <sascha.bischoff@arm.com>,
Mark Brown <broonie@kernel.org>
Subject: [PATCH 03/15] arm64: Fix field references for ICH_PPI_DVIR[01]_EL2
Date: Thu, 26 Mar 2026 15:35:18 +0000 [thread overview]
Message-ID: <20260326153530.3981879-4-maz@kernel.org> (raw)
In-Reply-To: <20260326153530.3981879-1-maz@kernel.org>
The ICH_PPI_DVIR[01]_EL2 registers should refer to the ICH_PPI_DVIRx_EL2
fields, instead of ICH_PPI_DVIx_EL2.
Fixes: 2808a8337078f ("arm64/sysreg: Add remaining GICv5 ICC_ & ICH_ sysregs for KVM support")
Link: https://sashiko.dev/#/patchset/20260319154937.3619520-1-sascha.bischoff%40arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/tools/sysreg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 51dcca5b2fa6e..3b57cb692c5be 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -4888,11 +4888,11 @@ Field 0 DVI0
EndSysregFields
Sysreg ICH_PPI_DVIR0_EL2 3 4 12 10 0
-Fields ICH_PPI_DVIx_EL2
+Fields ICH_PPI_DVIRx_EL2
EndSysreg
Sysreg ICH_PPI_DVIR1_EL2 3 4 12 10 1
-Fields ICH_PPI_DVIx_EL2
+Fields ICH_PPI_DVIRx_EL2
EndSysreg
SysregFields ICH_PPI_ENABLERx_EL2
--
2.47.3
next prev parent reply other threads:[~2026-03-26 15:35 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-26 15:35 [PATCH 00/15] KVM: arm64: First batch of vgic-v5 related fixes Marc Zyngier
2026-03-26 15:35 ` [PATCH 01/15] KVM: arm64: vgic: Don't reset cpuif/redist addresses at finalize time Marc Zyngier
2026-03-26 15:35 ` [PATCH 02/15] KVM: arm64: Don't skip per-vcpu NV initialisation Marc Zyngier
2026-03-26 15:35 ` Marc Zyngier [this message]
2026-03-26 15:35 ` [PATCH 04/15] KVM: arm64: Fix writeable mask for ID_AA64PFR2_EL1 Marc Zyngier
2026-03-26 15:35 ` [PATCH 05/15] KVM: arm64: Account for RESx bits in __compute_fgt() Marc Zyngier
2026-03-26 15:35 ` [PATCH 06/15] KVM: arm64: vgic-v5: Hold config_lock while finalizing GICv5 PPIs Marc Zyngier
2026-03-26 15:35 ` [PATCH 07/15] KVM: arm64: vgic-v5: Transfer edge pending state to ICH_PPI_PENDRx_EL2 Marc Zyngier
2026-03-26 15:35 ` [PATCH 08/15] KVM: arm64: vgic-v5: Cast vgic_apr to u32 to avoid undefined behaviours Marc Zyngier
2026-03-26 15:35 ` [PATCH 09/15] KVM: arm64: vgic-v5: align priority comparison with other GICs Marc Zyngier
2026-03-31 15:09 ` Sascha Bischoff
2026-03-31 17:18 ` Marc Zyngier
2026-04-01 8:18 ` Sascha Bischoff
2026-03-26 15:35 ` [PATCH 10/15] KVM: arm64: vgic-v5: Correctly set dist->ready once initialised Marc Zyngier
2026-03-26 15:35 ` [PATCH 11/15] KVM: arm64: Kill arch_timer_context::direct field Marc Zyngier
2026-03-26 15:35 ` [PATCH 12/15] KVM: arm64: Remove evaluation of timer state in kvm_cpu_has_pending_timer() Marc Zyngier
2026-03-31 15:44 ` Sascha Bischoff
2026-03-31 17:02 ` Marc Zyngier
2026-04-01 8:21 ` Sascha Bischoff
2026-03-26 15:35 ` [PATCH 13/15] KVM: arm64: Move GICv5 timer PPI validation into timer_irqs_are_valid() Marc Zyngier
2026-03-26 15:35 ` [PATCH 14/15] KVM: arm64: Correctly plumb ID_AA64PFR2_EL1 into pkvm idreg handling Marc Zyngier
2026-03-26 15:35 ` [PATCH 15/15] KVM: arm64: Don't advertises GICv3 in ID_PFR1_EL1 if AArch32 isn't supported Marc Zyngier
2026-03-30 17:05 ` [PATCH 00/15] KVM: arm64: First batch of vgic-v5 related fixes Mark Brown
2026-03-31 16:34 ` Sascha Bischoff
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