From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EA4C3264CE for ; Mon, 30 Mar 2026 14:49:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774882191; cv=none; b=EwbI9iuN9JjTuH5zag+VDCtIKIdLcP+DKRidHWQPCckS1CIpCHzS/JlH8fJTXRBMRjCAVVexQuURR2zgtlwGaQZhHcZffgt+UZtSFODk+ChqBfUl1uHY4H93+dD5Sw9Di2q1zFzejegMsmODL+GYY/qAIqi3r6s3Lb5QI0YtcQs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774882191; c=relaxed/simple; bh=ogU9AKOUaT35sbK8mPxNvogWxla2rweipWB00VFORvc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rLlc/J7bFavTgQ4H96FPNWmKz6MDX++U9bhaYwUkDSznOBEQNaD1CTgxH/CquWqkPKi8P5HrTUVh0yoMRiQ2oz+bns8WzyOnf1IKu/DMfjob4uGIl+NNOOjgy+rF1vy7W2ywR+HqFaNewvijoo46hduTQ7CETSUqXU/4fj+N0Hs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NMnNL2WM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NMnNL2WM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F5F9C4CEF7; Mon, 30 Mar 2026 14:49:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774882190; bh=ogU9AKOUaT35sbK8mPxNvogWxla2rweipWB00VFORvc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NMnNL2WMe7uDe3uyNNKfnO/XpOcf0kPrt79ADkN5IDlQa6wWQUQF9RqZmcdffxIul RyAKZWTuiCXPSrn1SXkekHEB9gMtK+lDJaaaa/0/BSvaYkL8jZRVaFmdJVrphYjrlr 6P2Xpi7UInitIaR7gB3gK/BH/79/thTyN4bW32/DohKGrWonmR3mp/qCi0h7uTThnL kIhoX2qJqw03dSyGb6gkNpYMuTCWGVuDE6CRoO3k9PVCktqGwbAUD9UF3CibvtDtUb uuZzGJXhmDh98tlEaRo3Nht1XkXpcstRTU1mTuVD5+upShfHP6giDgfX5/2AoSOrgP kjJBlVsbTliLw== From: Will Deacon To: kvmarm@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org, Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Quentin Perret , Fuad Tabba , Vincent Donnefort , Mostafa Saleh , Alexandru Elisei Subject: [PATCH v5 18/38] KVM: arm64: Support translation faults in inject_host_exception() Date: Mon, 30 Mar 2026 15:48:19 +0100 Message-ID: <20260330144841.26181-19-will@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260330144841.26181-1-will@kernel.org> References: <20260330144841.26181-1-will@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Extend inject_host_exception() to support the injection of translation faults on both the data and instruction side to 32-bit and 64-bit EL0 as well as 64-bit EL1. This will be used in a subsequent patch when resolving an unhandled host stage-2 abort. Cc: Fuad Tabba Reviewed-by: Fuad Tabba Tested-by: Fuad Tabba Tested-by: Mostafa Saleh Signed-off-by: Will Deacon --- arch/arm64/kvm/hyp/include/nvhe/trap_handler.h | 2 ++ arch/arm64/kvm/hyp/nvhe/hyp-main.c | 18 +++++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h b/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h index ba5382c12787..32d7b7746e8e 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h +++ b/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h @@ -16,4 +16,6 @@ __always_unused int ___check_reg_ ## reg; \ type name = (type)cpu_reg(ctxt, (reg)) +void inject_host_exception(u64 esr); + #endif /* __ARM64_KVM_NVHE_TRAP_HANDLER_H__ */ diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index adfc0bc15398..6db5aebd92dc 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -705,15 +705,24 @@ static void handle_host_smc(struct kvm_cpu_context *host_ctxt) kvm_skip_host_instr(); } -static void inject_host_exception(u64 esr) +void inject_host_exception(u64 esr) { u64 sctlr, spsr_el1, spsr_el2, exc_offset = except_type_sync; const u64 spsr_mask = PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT | PSR_DIT_BIT | PSR_PAN_BIT; - exc_offset += CURRENT_EL_SP_ELx_VECTOR; - spsr_el1 = spsr_el2 = read_sysreg_el2(SYS_SPSR); + switch (spsr_el1 & (PSR_MODE_MASK | PSR_MODE32_BIT)) { + case PSR_MODE_EL0t: + exc_offset += LOWER_EL_AArch64_VECTOR; + break; + case PSR_MODE_EL0t | PSR_MODE32_BIT: + exc_offset += LOWER_EL_AArch32_VECTOR; + break; + default: + exc_offset += CURRENT_EL_SP_ELx_VECTOR; + } + spsr_el2 &= spsr_mask; spsr_el2 |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h; @@ -728,6 +737,9 @@ static void inject_host_exception(u64 esr) if (system_supports_mte()) spsr_el2 |= PSR_TCO_BIT; + if (esr_fsc_is_translation_fault(esr)) + write_sysreg_el1(read_sysreg_el2(SYS_FAR), SYS_FAR); + write_sysreg_el1(esr, SYS_ESR); write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR); write_sysreg_el1(spsr_el1, SYS_SPSR); -- 2.53.0.1018.g2bb0e51243-goog