[PATCH v1 03/16] drm/i915/buf_trans: describe VS/PE Override layout

["Michał Grzelak" <michal.grzelak@intel.com>]

Name indices of each present VS/PE Override table. Reflect tables'
layout by grouping indices into enums. Pack & unify all enums into union
ddi_vswing_preemph_index.

Naming of the data structures is far from perfect and should be a
subject to renaming.

Capture Vswing / Preemphasis Override tables' layout from MTL onward.
Add a placeholder for ICL+.

Signed-off-by: Michał Grzelak <michal.grzelak@intel.com>
---
 .../drm/i915/display/intel_ddi_buf_trans.h    | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index bea6fb2ec6f4..20bf1d749344 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -74,6 +74,41 @@ struct intel_ddi_buf_trans {
 	u8 hdmi_default_entry;
 };
 
+enum lt_vswing_preemph_index {
+        XE3P_VS_PE_UNSET = -1,
+	XE3P_VS_PE_DEFAULT = 0,
+        XE3P_VS_PE_EDP = 3,
+        XE3P_VS_PE_DP14 = 4,
+        XE3P_VS_PE_DP21 = 5
+};
+
+enum snps_vswing_preemph_index {
+        MTL_C10_VS_PE_UNSET = -1,
+        MTL_C10_VS_PE_DP14_RBR_HBR = 0,
+        MTL_C10_VS_PE_DP14_HBR2_HBR3 = 1,
+        MTL_C10_VS_PE_EDP_NON_HBR3 = 2,
+        MTL_C10_VS_PE_EDP_HBR3 = 3,
+
+        MTL_C20_VS_PE_DP14 = 4,
+        MTL_C20_VS_PE_DP20 = 5
+};
+
+enum icl_vswing_preemph_index {
+        ICL_VS_PE_UNSET = -1,
+        ICL_VS_PE_DEFAULT = 0
+};
+
+union ddi_vswing_preemph_index {
+        enum lt_vswing_preemph_index lt;
+        enum snps_vswing_preemph_index snps;
+        enum icl_vswing_preemph_index icl;
+};
+
+struct ddi_vswing_preemph {
+        struct intel_ddi_buf_trans *buf_trans;
+        union ddi_vswing_preemph_index index;
+};
+
 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table);
 
 void intel_ddi_buf_trans_init(struct intel_encoder *encoder);
-- 
2.45.2