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Wed, 1 Apr 2026 01:02:34 +0000 Received: from DS2PR12MB9567.namprd12.prod.outlook.com ([fe80::636:1b52:24ca:d7e5]) by DS2PR12MB9567.namprd12.prod.outlook.com ([fe80::636:1b52:24ca:d7e5%3]) with mapi id 15.20.9769.015; Wed, 1 Apr 2026 01:02:34 +0000 From: Nathan Chen To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Yi Liu , Eric Auger , Zhenzhong Duan , Peter Maydell , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Zhao Liu , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Shameer Kolothum , Matt Ochs , Nicolin Chen , Nathan Chen Subject: [PATCH 00/11] hw/arm/smmuv3-accel: Resolve AUTO properties Date: Tue, 31 Mar 2026 18:02:20 -0700 Message-ID: <20260401010231.4166776-1-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SJ0PR13CA0184.namprd13.prod.outlook.com (2603:10b6:a03:2c3::9) To DS2PR12MB9567.namprd12.prod.outlook.com (2603:10b6:8:27c::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PR12MB9567:EE_|CH1PR12MB9647:EE_ X-MS-Office365-Filtering-Correlation-Id: 1011bd58-4a0a-4fe5-81f7-08de8f8a5bbb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=nathanc@nvidia.com; helo=DM1PR04CU001.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi, This series introduces support for resolving 'auto' for arm-smmuv3 accelerated mode's ATS, RIL, SSIDSIZE, and OAS feature properties based on host IOMMU capabilities. This is dependent on the series [1] for changing these property types to accept 'auto' values. Accelerated SMMUv3 Address Translation Services support is derived from IDR0, Range Invalidation support is derived from IDR3, Substream ID size is derived from IDR1, and output address space is derived from IDR5. Additionally, an OnOffAuto "ats" property is added for vfio-pci devices, where setting 'auto' detects the per-device presence of IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED from the kernel, and the ATS cap can be advertised or hidden by setting 'on' or 'off'. This is dependent on Shameer's recent kernel series for reporting effective ATS support status [2]. The default values are set to 'auto' for all properties. A complete branch can be found here: https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve Please take a look and let me know your feedback. Thanks, Nathan [0] https://lore.kernel.org/qemu-devel/20260309192119.870186-1-nathanc@nvidia.com/ [1] https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-nathanc@nvidia.com/ [2] https://lore.kernel.org/all/20260317111603.101456-1-skolothumtho@nvidia.com/ Example usage: qemu-system-aarch64 \ -object iommufd,id=iommufd0 \ -machine virt,accel=kvm,gic-version=3,ras=on,highmem-mmio-size=4T \ -cpu host -smp cpus=4 -m size=16G -nographic \ -object memory-backend-ram,size=16G,id=m0 \ -numa node,memdev=m0,cpus=0-3,nodeid=0 \ -numa node,nodeid=1 -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 \ -numa node,nodeid=5 -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 \ -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0,numa_node=0 \ -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1,accel=on,ats=auto,ssidsize=auto,ril=auto,oas=auto \ -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,io-reserve=0 \ -device vfio-pci-nohotplug,host=0009:06:00.0,bus=pcie.port1,rombar=0,id=dev0,iommufd=iommufd0,ats=auto \ -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=1 \ -object acpi-generic-initiator,id=gi1,pci-dev=dev0,node=2 \ -object acpi-generic-initiator,id=gi2,pci-dev=dev0,node=3 \ -object acpi-generic-initiator,id=gi3,pci-dev=dev0,node=4 \ -object acpi-generic-initiator,id=gi4,pci-dev=dev0,node=5 \ -object acpi-generic-initiator,id=gi5,pci-dev=dev0,node=6 \ -object acpi-generic-initiator,id=gi6,pci-dev=dev0,node=7 \ -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=8 \ -bios /usr/share/AAVMF/AAVMF_CODE.fd \ -device nvme,drive=nvme0,serial=deadbeaf1,bus=pcie.0 \ -drive file=/var/lib/libvirt/images/guest.qcow2,index=0,media=disk,format=qcow2,if=none,id=nvme0 \ -device e1000,romfile=/usr/local/share/qemu/efi-e1000.rom,netdev=net0,bus=pcie.0 \ -netdev user,id=net0,hostfwd=tcp::5558-:22,hostfwd=tcp::5586-:5586 Testing: Basic sanity testing was performed on an NVIDIA Grace platform with GPU device assignment and running CUDA test apps on the guest. Observed the feature properties being set based on host IOMMU capabilities and the ATS capability for a vfio-pci device reported based on what was reported from the host. Verified that the VM boot will fail without a cold-plugged device, and that a hot-plugged device re-uses the resolved values from the initial cold-plug. Additional testing and feedback are welcome. Nathan Chen (11): hw/arm/smmuv3-accel: Add helper for resolving auto parameters hw/arm/smmuv3-accel: Implement "auto" value for "ats" hw/arm/smmuv3: Change the default ats support to match the host vfio/pci: Add ats property and mask ATS cap when not exposed hw/arm/smmuv3-accel: Implement "auto" value for "ril" hw/arm/smmuv3: Change the default ril support to match the host hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize" hw/arm/smmuv3: Change the default ssidsize to match the host hw/arm/smmuv3-accel: Implement "auto" value for "oas" hw/arm/smmuv3: Change the default oas to match the host qemu-options.hx: Support "auto" for accel SMMUv3 properties backends/iommufd.c | 15 +++++++ hw/arm/smmuv3-accel.c | 50 +++++++++++++++++++++++- hw/arm/smmuv3-accel.h | 2 + hw/arm/smmuv3.c | 61 +++++++++++++++++------------ hw/core/machine.c | 8 ++++ hw/vfio/pci.c | 63 ++++++++++++++++++++++++++++++ hw/vfio/pci.h | 1 + include/hw/arm/smmuv3.h | 2 + include/system/host_iommu_device.h | 10 +++++ qemu-options.hx | 1 - 10 files changed, 185 insertions(+), 28 deletions(-) -- 2.43.0