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Tsirkin" , Pedro Barbuda , Mohamed Mediouni , Paolo Bonzini , Zhao Liu , Roman Bolshakov , Wei Liu , Phil Dennis-Jordan Subject: [PATCH v11 09/15] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off Date: Mon, 13 Apr 2026 18:52:11 +0200 Message-ID: <20260413165217.47105-10-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260413165217.47105-1-mohamed@unpredictable.fr> References: <20260413165217.47105-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEzMDE2NiBTYWx0ZWRfX6zFErk4EPOCV +DAAWpqD8GwgfOYTwb1hOsw0rLknLex7ycVMK/3K+1gZmGlb6VwwqHoX8asDZoiHNUhkrj/WpWz UIM5lbzetpRZadGAcvchACx8qJWfwFqHEjzrx9iAUbxevePCz6DpcSU+xxo1IhJ9HtYYFQVb3qK gWQv0YBR3uwKlceeVE0aCZoxWuSRGegayzsFKaLKSjnfc3bq6FWyoHgeeoLy0PqPM3gYI//hBrr NDKiI6YGg4MHimxT8XUfYurH/CFYxAKoICYavylduiH42RXN3+/e17/pUg8jjrhEZFdPqnqa6/R IodlR9tX78wJevHPfSAfG9rMGsZuOZEokKGWAQ5MPEGQBO5Fm6r9rrL8u2GKLw= X-Authority-Info-Out: v=2.4 cv=P/43RyAu c=1 sm=1 tr=0 ts=69dd1f81 cx=c_apl:c_pps:t_out a=9OgfyREA4BUYbbCgc0Y0oA==:117 a=9OgfyREA4BUYbbCgc0Y0oA==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=4IdwVP5-j8YZXVcKM5MA:9 X-Proofpoint-ORIG-GUID: r_L7CJjCsWBVSeX5kxB0QavXvxwawOTp X-Proofpoint-GUID: r_L7CJjCsWBVSeX5kxB0QavXvxwawOTp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-13_03,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 suspectscore=0 malwarescore=0 mlxlogscore=867 spamscore=0 adultscore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2604130166 Received-SPF: pass client-ip=57.103.68.156; envelope-from=mohamed@unpredictable.fr; helo=outbound.mr.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When kernel-irqchip=on, manage TPR as part of the APIC state instead entirely. This fixes some failure to set state errors. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 62542922a4..74b94b799e 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -95,7 +95,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] = { WHvX64RegisterCr2, WHvX64RegisterCr3, WHvX64RegisterCr4, - WHvX64RegisterCr8, /* X64 Debug Registers */ /* @@ -459,8 +458,11 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level) vcxt.values[idx++].Reg64 = env->cr[3]; assert(whpx_register_names[idx] == WHvX64RegisterCr4); vcxt.values[idx++].Reg64 = env->cr[4]; - assert(whpx_register_names[idx] == WHvX64RegisterCr8); - vcxt.values[idx++].Reg64 = vcpu->tpr; + /* For kernel-irqchip=on, TPR is managed as part of APIC state */ + if (!whpx_irqchip_in_kernel()) { + WHV_REGISTER_VALUE cr8 = {.Reg64 = vcpu->tpr}; + whpx_set_reg(cpu, WHvX64RegisterCr8, cr8); + } /* 8 Debug Registers - Skipped */ @@ -716,11 +718,14 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level) env->cr[3] = vcxt.values[idx++].Reg64; assert(whpx_register_names[idx] == WHvX64RegisterCr4); env->cr[4] = vcxt.values[idx++].Reg64; - assert(whpx_register_names[idx] == WHvX64RegisterCr8); - tpr = vcxt.values[idx++].Reg64; - if (tpr != vcpu->tpr) { - vcpu->tpr = tpr; - cpu_set_apic_tpr(x86_cpu->apic_state, tpr); + + /* For kernel-irqchip=on, TPR is managed as part of APIC state */ + if (!whpx_irqchip_in_kernel()) { + tpr = vcpu->exit_ctx.VpContext.Cr8; + if (tpr != vcpu->tpr) { + vcpu->tpr = tpr; + cpu_set_apic_tpr(x86_cpu->apic_state, tpr); + } } /* 8 Debug Registers - Skipped */ @@ -1660,7 +1665,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) /* Sync the TPR to the CR8 if was modified during the intercept */ tpr = cpu_get_apic_tpr(x86_cpu->apic_state); - if (tpr != vcpu->tpr) { + if (!whpx_irqchip_in_kernel() && tpr != vcpu->tpr) { vcpu->tpr = tpr; reg_values[reg_count].Reg64 = tpr; qatomic_set(&cpu->exit_request, true); @@ -1702,12 +1707,14 @@ static void whpx_vcpu_post_run(CPUState *cpu) env->eflags = vcpu->exit_ctx.VpContext.Rflags; - uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8; - if (vcpu->tpr != tpr) { - vcpu->tpr = tpr; - bql_lock(); - cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr); - bql_unlock(); + if (!whpx_irqchip_in_kernel()) { + uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8; + if (vcpu->tpr != tpr) { + vcpu->tpr = tpr; + bql_lock(); + cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr); + bql_unlock(); + } } vcpu->interruption_pending = -- 2.50.1 (Apple Git-155)