From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2545339BFE8 for ; Fri, 17 Apr 2026 12:46:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776429979; cv=none; b=pdqV46kocIOz6g9YY2MSTAqLNN2utpt8s9Gz79Zt72PiDzUq+FJU5G+qdvUBS1PNQ0duc3Yse0Wez2K7rIj12wEVvaGtOrr7x+KvdtZWA2HXYNm+gbatlfplD1QsxYqb6Ug2gpuYAEz20zBWQt8NoRZE+WhzcKnhI+1LDnHBj/c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776429979; c=relaxed/simple; bh=nDVq5uxP1KAWX6hBUY8jiqpUC+dmduipcQvQoFbJMng=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DSFYw5y7nCoaFGiGspes84fjzX6Z8vsI64E0j4oB85oeA7yjhnVwfn54Adjy0yQ7FBhI58gTZ9wU0XDz14Fs9F822z92L0l/z5Amn4nWBZyZsr0JrB/f3LGKYrPhf9dfNd/DhCcUK9z1Wc3quD04A8aNCMbG4ODitoteM9K4JOA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nx0dFhSr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nx0dFhSr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 01D50C2BCB6; Fri, 17 Apr 2026 12:46:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776429979; bh=nDVq5uxP1KAWX6hBUY8jiqpUC+dmduipcQvQoFbJMng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nx0dFhSrT4gBZFmbWcGyBgmtjhHfGCbmaoCMWXpJOuviLnyTgFx58d2QiV+OALJ4n IVyGo00dVvIRPXXzBbuIavLAtSKjFG3SQOHYHQoeUWpjD11xWY2YT2MQP0nefGJ2nC nzHANJrLAOL3qbenGnY9WYuca43XFoivWWSN/kChKfwcoKbiQw6rOxEX2PqdLRRLll AyEO0rq512yJyXnA+RtDW4WC2JHaZacU6T99NcMcBZc0bYlheGhLhUCtktsl6iYOaG JjrWcQBqI+QnfD16/VgpXOjVL/mYgOyijZKOAyOa0W/6qcEu5QQqmTtb9A/2oTupKI FRXvWmv5dzQYg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wDiaO-0000000CRo5-3qyd; Fri, 17 Apr 2026 12:46:17 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Deepanshu Kartikey , Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: [PATCH 2/4] KVM: arm64: timer: Kill the per-timer level cache Date: Fri, 17 Apr 2026 13:46:10 +0100 Message-ID: <20260417124612.2770268-3-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260417124612.2770268-1-maz@kernel.org> References: <20260417124612.2770268-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kartikey406@gmail.com, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false The timer code makes use of a per-timer irq level cache, which looks like a very minor optimisation to avoid taking a lock upon updating the GIC view of the interrupt when it is unchanged from the previous state. This is coming in the way of more important correctness issues, so get rid of the cache, which simplifies a couple of minor things. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/arch_timer.c | 18 +++++++++--------- include/kvm/arm_arch_timer.h | 5 ----- 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index d6802fc87e085..fdc1afff06340 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -446,9 +446,8 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, { kvm_timer_update_status(timer_ctx, new_level); - timer_ctx->irq.level = new_level; trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_irq(timer_ctx), - timer_ctx->irq.level); + new_level); if (userspace_irqchip(vcpu->kvm)) return; @@ -466,7 +465,7 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, kvm_vgic_inject_irq(vcpu->kvm, vcpu, timer_irq(timer_ctx), - timer_ctx->irq.level, + new_level, timer_ctx); } @@ -477,8 +476,7 @@ static void timer_emulate(struct arch_timer_context *ctx) trace_kvm_timer_emulate(ctx, pending); - if (pending != ctx->irq.level) - kvm_timer_update_irq(timer_context_to_vcpu(ctx), pending, ctx); + kvm_timer_update_irq(timer_context_to_vcpu(ctx), pending, ctx); kvm_timer_update_status(ctx, pending); @@ -677,6 +675,7 @@ static inline void set_timer_irq_phys_active(struct arch_timer_context *ctx, boo static void kvm_timer_vcpu_load_gic(struct arch_timer_context *ctx) { struct kvm_vcpu *vcpu = timer_context_to_vcpu(ctx); + bool pending = kvm_timer_pending(ctx); bool phys_active = false; /* @@ -685,12 +684,12 @@ static void kvm_timer_vcpu_load_gic(struct arch_timer_context *ctx) * this point and the register restoration, we'll take the * interrupt anyway. */ - kvm_timer_update_irq(vcpu, kvm_timer_pending(ctx), ctx); + kvm_timer_update_irq(vcpu, pending, ctx); if (irqchip_in_kernel(vcpu->kvm)) phys_active = kvm_vgic_map_is_active(vcpu, timer_irq(ctx)); - phys_active |= ctx->irq.level; + phys_active |= pending; phys_active |= vgic_is_v5(vcpu->kvm); set_timer_irq_phys_active(ctx, phys_active); @@ -699,6 +698,7 @@ static void kvm_timer_vcpu_load_gic(struct arch_timer_context *ctx) static void kvm_timer_vcpu_load_nogic(struct kvm_vcpu *vcpu) { struct arch_timer_context *vtimer = vcpu_vtimer(vcpu); + bool pending = kvm_timer_pending(vtimer); /* * Update the timer output so that it is likely to match the @@ -706,7 +706,7 @@ static void kvm_timer_vcpu_load_nogic(struct kvm_vcpu *vcpu) * this point and the register restoration, we'll take the * interrupt anyway. */ - kvm_timer_update_irq(vcpu, kvm_timer_pending(vtimer), vtimer); + kvm_timer_update_irq(vcpu, pending, vtimer); /* * When using a userspace irqchip with the architected timers and a @@ -718,7 +718,7 @@ static void kvm_timer_vcpu_load_nogic(struct kvm_vcpu *vcpu) * being de-asserted, we unmask the interrupt again so that we exit * from the guest when the timer fires. */ - if (vtimer->irq.level) + if (pending) disable_percpu_irq(host_vtimer_irq); else enable_percpu_irq(host_vtimer_irq, host_vtimer_irq_flags); diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index bf8cc9589bd09..2c26d457c3510 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -66,11 +66,6 @@ struct arch_timer_context { */ bool loaded; - /* Output level of the timer IRQ */ - struct { - bool level; - } irq; - /* Who am I? */ enum kvm_arch_timers timer_id; -- 2.47.3