From: Raag Jadav <raag.jadav@intel.com>
To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
netdev@vger.kernel.org
Cc: simona.vetter@ffwll.ch, airlied@gmail.com, kuba@kernel.org,
lijo.lazar@amd.com, Hawking.Zhang@amd.com, davem@davemloft.net,
pabeni@redhat.com, edumazet@google.com, maarten@lankhorst.se,
zachary.mckevitt@oss.qualcomm.com, rodrigo.vivi@intel.com,
riana.tauro@intel.com, michal.wajdeczko@intel.com,
matthew.d.roper@intel.com, umesh.nerlige.ramappa@intel.com,
mallesh.koujalagi@intel.com, soham.purkait@intel.com,
anoop.c.vijay@intel.com, aravind.iddamsetty@linux.intel.com,
Raag Jadav <raag.jadav@intel.com>
Subject: [PATCH v1 06/11] drm/xe/sysctrl: Add system controller event support
Date: Sat, 18 Apr 2026 02:46:41 +0530 [thread overview]
Message-ID: <20260417211730.837345-7-raag.jadav@intel.com> (raw)
In-Reply-To: <20260417211730.837345-1-raag.jadav@intel.com>
System controller reports different types of events to GFX endpoint for
different usecases, add initial support for them. This will be further
extended to service those usecases.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_sysctrl.c | 11 +++
drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
drivers/gpu/drm/xe/xe_sysctrl_event.c | 86 +++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 57 ++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 18 ++++
drivers/gpu/drm/xe/xe_sysctrl_types.h | 3 +
7 files changed, 177 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 3fceda259834..1c863b711ae9 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -126,6 +126,7 @@ xe-y += xe_bb.o \
xe_survivability_mode.o \
xe_sync.o \
xe_sysctrl.o \
+ xe_sysctrl_event.o \
xe_sysctrl_mailbox.o \
xe_tile.o \
xe_tile_sysfs.o \
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 7de3e73bd8e0..6a7da5d2794a 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -12,6 +12,7 @@
#include "regs/xe_sysctrl_regs.h"
#include "xe_device.h"
#include "xe_mmio.h"
+#include "xe_pm.h"
#include "xe_soc_remapper.h"
#include "xe_sysctrl.h"
#include "xe_sysctrl_mailbox.h"
@@ -39,6 +40,12 @@ static void sysctrl_fini(void *arg)
static void xe_sysctrl_work(struct work_struct *work)
{
+ struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
+ struct xe_device *xe = sc_to_xe(sc);
+
+ guard(xe_pm_runtime)(xe);
+ guard(mutex)(&sc->work_lock);
+ xe_sysctrl_event(sc);
}
/**
@@ -74,6 +81,10 @@ int xe_sysctrl_init(struct xe_device *xe)
if (ret)
return ret;
+ ret = devm_mutex_init(xe->drm.dev, &sc->work_lock);
+ if (ret)
+ return ret;
+
xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
xe_sysctrl_mailbox_init(sc);
INIT_WORK(&sc->work, xe_sysctrl_work);
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index f7469bfc9324..090dffb6d55f 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -16,6 +16,7 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
return container_of(sc, struct xe_device, sc);
}
+void xe_sysctrl_event(struct xe_sysctrl *sc);
int xe_sysctrl_init(struct xe_device *xe);
void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
void xe_sysctrl_pm_resume(struct xe_device *xe);
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
new file mode 100644
index 000000000000..74163e0bafe2
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_device.h"
+#include "xe_irq.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_event_types.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+
+static void get_pending_event(struct xe_sysctrl *sc, struct xe_sysctrl_mailbox_command *command)
+{
+ struct xe_sysctrl_event_response *response = command->data_out;
+ struct xe_device *xe = sc_to_xe(sc);
+ u32 count = XE_SYSCTRL_EVENT_FLOOD;
+ size_t len;
+ int ret;
+
+ do {
+ memset(response, 0, sizeof(*response));
+
+ ret = xe_sysctrl_send_command(sc, command, &len);
+ if (ret) {
+ xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
+ return;
+ }
+
+ if (len != sizeof(*response)) {
+ xe_err(xe, "sysctrl: unexpected event response length %zu (expected %zu)\n",
+ len, sizeof(*response));
+ return;
+ }
+
+ if (response->event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED)
+ xe_warn(xe, "[RAS]: counter threshold crossed\n");
+ else
+ xe_err(xe, "sysctrl: unexpected event %#x\n", response->event);
+
+ if (!--count) {
+ xe_err(xe, "sysctrl: event flooding\n");
+ return;
+ }
+
+ xe_dbg(xe, "sysctrl: %u events pending\n", response->count);
+ } while (response->count);
+}
+
+static void event_request_prepare(struct xe_device *xe, struct xe_sysctrl_app_msg_hdr *header,
+ struct xe_sysctrl_event_request *request)
+{
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+ header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
+ REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
+
+ request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
+ request->fn = PCI_FUNC(pdev->devfn);
+}
+
+/**
+ * xe_sysctrl_event() - Handler for System Controller events
+ * @sc: System Controller instance
+ *
+ * Handle events generated by System Controller.
+ */
+void xe_sysctrl_event(struct xe_sysctrl *sc)
+{
+ struct xe_sysctrl_mailbox_command command = {};
+ struct xe_sysctrl_event_response response = {};
+ struct xe_sysctrl_event_request request = {};
+ struct xe_sysctrl_app_msg_hdr header = {};
+
+ xe_device_assert_mem_access(sc_to_xe(sc));
+ event_request_prepare(sc_to_xe(sc), &header, &request);
+
+ command.header = header;
+ command.data_in = &request;
+ command.data_in_len = sizeof(request);
+ command.data_out = &response;
+ command.data_out_len = sizeof(response);
+
+ get_pending_event(sc, &command);
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
new file mode 100644
index 000000000000..4d444ba40b9b
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
+#define _XE_SYSCTRL_EVENT_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_SYSCTRL_EVENT_DATA_LEN 59
+
+/* Modify as needed */
+#define XE_SYSCTRL_EVENT_FLOOD 16
+
+/**
+ * enum xe_sysctrl_event - Events reported by System Controller
+ *
+ * @XE_SYSCTRL_EVENT_THRESHOLD_CROSSED: Error counter threshold crossed
+ */
+enum xe_sysctrl_event {
+ XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 0x01,
+};
+
+/**
+ * struct xe_sysctrl_event_request - Request structure for pending event
+ */
+struct xe_sysctrl_event_request {
+ /** @vector: MSI-X vector that was triggered */
+ u32 vector;
+ /** @fn: Function index (0-7) of PCIe device */
+ u32 fn:8;
+ /** @reserved: Reserved for future use */
+ u32 reserved:24;
+ /** @reserved2: Reserved for future use */
+ u32 reserved2[2];
+} __packed;
+
+/**
+ * struct xe_sysctrl_event_response - Response structure for pending event
+ */
+struct xe_sysctrl_event_response {
+ /** @count: Pending event count, decremented by fw on each response */
+ u32 count;
+ /** @event: Pending event type */
+ u32 event;
+ /** @timestamp: Timestamp of most recent event */
+ u64 timestamp;
+ /** @extended: Event has extended payload */
+ u32 extended:1;
+ /** @reserved: Reserved for future use */
+ u32 reserved:31;
+ /** @data: Generic event data */
+ u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
+} __packed;
+
+#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index 89456aec6097..84d7c647e743 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -10,6 +10,24 @@
#include "abi/xe_sysctrl_abi.h"
+/**
+ * enum xe_sysctrl_group - System Controller command groups
+ *
+ * @XE_SYSCTRL_GROUP_GFSP: GFSP group
+ */
+enum xe_sysctrl_group {
+ XE_SYSCTRL_GROUP_GFSP = 0x01,
+};
+
+/**
+ * enum xe_sysctrl_gfsp_cmd - Commands supported by GFSP group
+ *
+ * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
+ */
+enum xe_sysctrl_gfsp_cmd {
+ XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
+};
+
/**
* struct xe_sysctrl_mailbox_command - System Controller mailbox command
*/
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
index 5f408d6491ef..95359af691c9 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -31,6 +31,9 @@ struct xe_sysctrl {
/** @work: Pending events worker */
struct work_struct work;
+
+ /** @work_lock: Mutex protecting pending events */
+ struct mutex work_lock;
};
#endif
--
2.43.0
next prev parent reply other threads:[~2026-04-17 21:21 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-17 21:16 [PATCH v1 00/11] Introduce error threshold to drm_ras Raag Jadav
2026-04-17 21:16 ` [PATCH v1 01/11] drm/ras: Update counter helpers with counter naming Raag Jadav
2026-04-17 21:16 ` [PATCH v1 02/11] drm/ras: Introduce get-error-threshold Raag Jadav
2026-04-22 5:49 ` Tauro, Riana
2026-04-22 6:21 ` Raag Jadav
2026-04-17 21:16 ` [PATCH v1 03/11] drm/ras: Introduce set-error-threshold Raag Jadav
2026-04-22 6:12 ` Tauro, Riana
2026-04-17 21:16 ` [PATCH v1 04/11] drm/xe/uapi: Add additional error components to XE drm_ras Raag Jadav
2026-04-17 21:16 ` [PATCH v1 05/11] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
2026-04-22 5:55 ` Tauro, Riana
2026-04-22 6:25 ` Raag Jadav
2026-04-17 21:16 ` Raag Jadav [this message]
2026-04-17 21:16 ` [PATCH v1 07/11] drm/xe/ras: Introduce correctable error handling Raag Jadav
2026-04-17 21:16 ` [PATCH v1 08/11] drm/xe/ras: Get error threshold support Raag Jadav
2026-05-11 17:10 ` Tauro, Riana
2026-05-12 14:37 ` Raag Jadav
2026-04-17 21:16 ` [PATCH v1 09/11] drm/xe/ras: Set " Raag Jadav
2026-05-11 17:21 ` Tauro, Riana
2026-05-12 14:44 ` Raag Jadav
2026-05-12 16:52 ` Raag Jadav
2026-04-17 21:16 ` [PATCH v1 10/11] drm/xe/drm_ras: Wire up error threshold callbacks Raag Jadav
2026-05-11 17:30 ` Tauro, Riana
2026-04-17 21:16 ` [PATCH v1 11/11] drm/xe/ras: Add flag for Xe RAS Raag Jadav
2026-04-30 14:24 ` Tauro, Riana
2026-04-20 19:51 ` ✗ CI.checkpatch: warning for Introduce error threshold to drm_ras Patchwork
2026-04-20 19:52 ` ✓ CI.KUnit: success " Patchwork
2026-04-20 21:04 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-21 0:01 ` ✗ Xe.CI.FULL: failure " Patchwork
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