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Tsirkin" , Peter Maydell , Zhao Liu Subject: [PATCH v2 13/38] whpx: i386: interrupt priority support Date: Mon, 20 Apr 2026 12:42:23 +0200 Message-ID: <20260420104248.86702-14-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260420104248.86702-1-mohamed@unpredictable.fr> References: <20260420104248.86702-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: -SxLM4dJTJev-AiykB4STG2w6MD6DZ2D X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDEwNCBTYWx0ZWRfX3XW3xQb9Sawf Tg+P5z5Rk9A7r1oWnc+UMoM6rGN9bQ8azLXr87OKJMuJa1mnJBqOW/euElhCBIHorP77aK9leJ/ qf/ubyItpyQfrKpi8sKTF8l0U+3k8Hmdcm83d/PsQIQPVH99rF7XgqOC8rZkva1OMSm7zJ+1Dnl BndrJ6h7QV4ckod3IGuLduBDuNsxjsKMehDrOPCJX0DCTLgrY8N/8cy09/C6fEcbZn2uP0RHI48 vDqn2W0yv39OGfq4xKj/Hb3bp83u1GZViNsvCFQTQaYibGGL+vsiaXe2J6AWFRhKqwtcGfyVk1f qyFuhohJ037yOCni4WVpllI13p7QiYkzJcDC8KNIW3ZLK7ODvA0y5xhB0jZenM= X-Proofpoint-ORIG-GUID: -SxLM4dJTJev-AiykB4STG2w6MD6DZ2D X-Authority-Info-Out: v=2.4 cv=ce7fb3DM c=1 sm=1 tr=0 ts=69e6034f cx=c_apl:c_pps:t_out a=qkKslKyYc0ctBTeLUVfTFg==:117 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=NuKELtICf0aykZwt-QIA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-20_02,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=687 bulkscore=0 adultscore=0 mlxscore=0 suspectscore=0 clxscore=1030 phishscore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2604200104 Received-SPF: pass client-ip=57.103.72.83; envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Implement APIC IRR interrupt priorities. Even with kernel-irqchip=off, Hyper-V is aware of interrupt priorities and implements CR8/TPR, with the InterruptPriority field being followed. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index d38b83d274..930731e4bf 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -1588,6 +1588,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) UINT32 reg_count = 0; WHV_REGISTER_VALUE reg_values[3]; WHV_REGISTER_NAME reg_names[3]; + int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); memset(&new_int, 0, sizeof(new_int)); memset(reg_values, 0, sizeof(reg_values)); @@ -1623,10 +1624,20 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } } + if (irr == -1) { + if (isa_pic != NULL && pic_get_output(isa_pic)) { + /* In case it's a PIC interrupt */ + irr = 0; + } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { + abort(); + } + } + /* Get pending hard interruption or replay one that was overwritten */ if (!whpx_irqchip_in_kernel()) { if (!vcpu->interruption_pending && - vcpu->interruptable && (env->eflags & IF_MASK)) { + vcpu->interruptable && (env->eflags & IF_MASK) + && (vcpu->tpr < irr || irr == 0)) { assert(!new_int.InterruptionPending); if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); @@ -1683,13 +1694,17 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } /* Update the state of the interrupt delivery notification */ - if (!vcpu->window_registered && + if ((!vcpu->window_registered || + (vcpu->window_priority < irr && vcpu->window_priority != 0) || + (irr == 0 && vcpu->window_priority != 0)) && cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { reg_values[reg_count].DeliverabilityNotifications = (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) { - .InterruptNotification = 1 + .InterruptNotification = 1, + .InterruptPriority = irr >> 4 }; vcpu->window_registered = 1; + vcpu->window_priority = irr; reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications; reg_count += 1; } @@ -1703,7 +1718,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) reg_names, reg_count, reg_values); if (FAILED(hr)) { error_report("WHPX: Failed to set interrupt state registers," - " hr=%08lx", hr); + " hr=%08lx, InterruptPriority=%i", hr, irr >> 4); } } } @@ -1919,6 +1934,7 @@ int whpx_vcpu_run(CPUState *cpu) case WHvRunVpExitReasonX64InterruptWindow: vcpu->ready_for_pic_interrupt = 1; vcpu->window_registered = 0; + vcpu->window_priority = 0; ret = 0; break; -- 2.50.1 (Apple Git-155)