From: Flaviu Nistor <flaviu.nistor@gmail.com>
To: u-boot@lists.denx.de
Cc: Vignesh R <vigneshr@ti.com>, Tom Rini <trini@konsulko.com>,
Takahiro Kuwano <Takahiro.Kuwano@infineon.com>,
Flaviu Nistor <flaviu.nistor@gmail.com>
Subject: [PATCH] mtd: spi-nor-ids: Add mt35xl256 and mtd35xu256 chips
Date: Mon, 20 Apr 2026 15:48:26 +0300 [thread overview]
Message-ID: <20260420124826.25876-1-flaviu.nistor@gmail.com> (raw)
Add mt35xl256aba and mtd35xu256aba chips to the
spi-nor id table.
Both chips have a size of 32MB where mt35xu256aba
is the 1.8V version and mt35xl256aba is the 3V
version.
Signed-off-by: Flaviu Nistor <flaviu.nistor@gmail.com>
---
drivers/mtd/spi/spi-nor-ids.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index e7fea375706..791e2677aed 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -371,6 +371,10 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_MT35XU
+ { INFO("mt35xl256aba", 0x2c5a19, 0, 128 * 1024, 256,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("mt35xu256aba", 0x2c5b19, 0, 128 * 1024, 256,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
{ INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
{ INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024,
--
2.43.0
reply other threads:[~2026-04-20 12:48 UTC|newest]
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